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CSD96370Q5M датащи(PDF) 6 Page - Texas Instruments |
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CSD96370Q5M датащи(HTML) 6 Page - Texas Instruments |
6 / 20 page CSD96370Q5M SLPS265C – NOVEMBER 2010 – REVISED OCTOBER 2011 www.ti.com ENABLE The ENABLE pin is TTL compatible. The logic level thresholds are sustained under all VDD operating conditions between VPOR to VDD. In addition, if this pin is left floating, a weak internal pull down resistor of 100kΩ will pull the ENABLE pin below the logic level low threshold. The operational functions of this pin should follow the timing diagram outlined in Figure 5. A logic level low will actively hold both Control FET and Sync FET gates low and VDD pin should typically draw less than 5µA. POWER UP SEQUENCING If the ENABLE signal is used, it is necessary to ensure proper co-ordination with the ENABLE and soft-start features of the external PWM controller in the system. If the CSD96370Q5M was disabled through ENABLE without sequencing with the PWM IC controller, the buck converter output will have no voltage or fall below regulation set point voltage. As a result, the PWM controller IC delivers Max duty cycle on the PWM line. If the Power Stage CSD96370Q5M is re-enabled by driving the ENABLE pin high, there will be an extremely large input inrush current when the output voltage builds back up again. The input inrush current might have undesirable consequences such as inductor saturation, driving the input power supply into current limit or even catastrophic failure of the CSD96370Q5M device. Disabling the PWM controller is recommended when the CSD96370Q5M is disabled. The PWM controller should always be re-enabled by going through soft-start routine to control and minimize the input inrush current and reduce current and voltage stress on all buck converter components. It is recommended that the external PWM controller be disabled when CSD96370Q5M is disabled or nonoperational because of UVLO. PWM The input PWM pin incorporates a 3-State function. The Control FET and Sync FET gates are forced low if the PWM pin is left floating for more than the 3-State Hold off time (t3HT), typically 100ns. This requires the source impedance of the driving PWM signal to be a minimum of 250k Ω when in 3-State mode. Operation in and out of 3-State mode should follow the timing diagram outlined in Figure 6. Both VPWML and VPWMH threshold levels are set to accommodate both 3.3V and 5V logic controllers. During normal operation, the PWM signal should be driven to logic levels Low and High with a maximum of 220 Ω/320Ω sink/source impedance respectively. GATE DRIVERS The CSD96370Q5M has an internal high-performance gate driver IC that ensures minimum MOSFET dead-time while eliminating potential shoot-through currents. Propagation delays between the Control FET and Sync FET gates are kept to a minimum to minimize body diode conduction and improve efficiency. The gate driver IC incorporates an adaptive shoot through protection scheme which ensures that neither MOSFET is turned on while the other one is still conducting at the same time, preventing cross conduction. See Table 1. Table 1. Truth Table CONTROL FET ENABLE PWM SYNC FET GATE VSW GATE L X L L 3-State H <Min ON time L L 3-State H L L H PGND H 3-State L L 3-State H H H L VIN L = Logic Low; H = Logic High; X = Don't care; minimum on time = 40ns START UP IN PRE-BIASED OUTPUT VOLTAGE The CSD96370Q5M incorporates a simple pre-bias feature to protect against the discharging of a prebiased output voltage and inducing large negative inductor currents. After the Power On Reset threshold is crossed and the ENABLE pin is set to logic level high, both internal MOSFETs are actively held low until the PWM pin receives a signal that crosses logic level high threshold and meets the minimum on time criteria (see the Electrical Characteristics Table). This allows the PWM control IC to provide a soft start routine that creates a monotonic startup of the output voltage. The pre-bias feature is enabled for a single event and subsequent PWM signals creates normal switching of the internal MOSFETs (see Table 1). To reactivate the pre-bias feature, the ENABLE pin needs to be pulled below logic level low or the VDD supply voltage needs to cross UVLO. 6 Copyright © 2010–2011, Texas Instruments Incorporated |
Аналогичный номер детали - CSD96370Q5M_15 |
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Аналогичное описание - CSD96370Q5M_15 |
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