SENSE1

1

FB1

2

COMP1

SS1

4

VDD

5

FREQ

6

SGND

7

EN

8

PGOOD

9

FPWM

10

SS2

11

COMP2

12

FB2

13

SENSE2

14

ILIM1

SW1

HDRV1

BOOT1

PGND1

LDRV1

VIN

V5

LDRV2

PGND2

BOOT2

HDRV2

SW2

ILIM2

3

28

27

26

25

24

23

22

21

20

19

18

17

16

15

5V

FPWM

VRON

R18

R17

POK

R20

R19

R1

C29

C16

(C15)

R22

(R16)

R21

(R15)

R23

(R14)

C17

(C14)

C25

(C22)

C26

(C23)

C31

C6 (C5)

C7 (C4)

R9 (R6)

R8 (R7)

Q2

(Q5)

Q1

(Q4)

C32

(C1)

L1

(L2)

Vo1

(Vo2)

D2

(D1)

C30

(C28)

FPWM

EN

PGOOD

FREQ

BOOT1 (2)

HDRV1 (2)

SW1 (2)

ILIM1 (2)

LDRV1 (2)

PGND1 (2)

SENSE1 (2)

V5

COMP1 (2)

FB1 (2)

SS1 (2)

SGND

LM2657

SNVS342B – JANUARY 2005 – REVISED MARCH 2013

www.ti.com

Typical Application (Channel 2 in parenthesis)

Connection Diagram

Figure 1. 28-Pin TSSOP (Top View)

See PW Package

PIN DESCRIPTION

Pin 1, SENSE1: Output voltage sense pin for Channel 1. It is tied directly to the output rail. The SENSE pin voltage is used by the IC,

together with the VIN voltage (Pin 22) to calculate the CCM (continuous conduction mode) duty cycle. This is used by the

IC to set the minimum duty cycle in the SKIP mode to 85% of the CCM value. It is also used to set the adaptive duty

cycle clamp (see Pin 3).

Pin 2, FB1:

Feedback pin for Channel 1. This is the inverting input of the channel’s error amplifier. The voltage on this pin under

regulation is nominally at 0.6V. A ‘Power Good window’ on this pin determines if the output voltage is within regulation

limits (±13%). If the voltage (on either channel) falls outside this window for more than 7µs, ‘Power Not Good’ is signaled

on the PGOOD pin (Pin 9). Additionally, if the FB voltage is above the upper limit, an over-voltage fault condition occurs

which turns on the low-side FET. The part will resume normal operation on the next high side cycle in which no fault is

detected. When single channel operation is desired (one channel is used, the other is disabled), the feedback pins of

both channels must be connected together, near the IC. All other pins specific to the unused channel should be left

floating (not connected to each other, either).

2

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