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TC7126ACKW датащи(PDF) 9 Page - Microchip Technology

номер детали TC7126ACKW
подробное описание детали  3-1/2 Digit Analog-to-Digital Converters
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

TC7126ACKW датащи(HTML) 9 Page - Microchip Technology

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© 2002 Microchip Technology Inc.
DS21458B-page 9
TC7126/A
3.0
DETAILED DESCRIPTION
(All Pin Designations Refer to 40-Pin PDIP.)
3.1
Dual Slope Conversion Principles
The TC7126A is a dual slope, integrating analog-to-
digital converter. An understanding of the dual slope
conversion technique will aid in following the detailed
TC7126/A operation theory.
The conventional dual slope converter measurement
cycle has two distinct phases:
• Input Signal Integration
• Reference Voltage Integration (De-integration)
The input signal being converted is integrated for a fixed
time period (TSI). Time is measured by counting clock
pulses. An opposite polarity constant reference voltage
is then integrated until the integrator output voltage
returns to zero. The reference integration time is directly
proportional to the input signal (TRI) (seeFigure3-1).
FIGURE 3-1:
BASIC DUAL SLOPE
CONVERTER
In a simple dual slope converter, a complete conver-
sion requires the integrator output to “ramp-up” and
“ramp-down.”
A simple mathematical equation relates the input sig-
nal, reference voltage and integration time:
EQUATION 3-1:
For a constant VIN:
EQUATION 3-2:
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as
they are stable during a measurement cycle. Noise
immunity is an inherent benefit. Noise spikes are inte-
grated or averaged to zero during integration periods.
Integrating ADCs are immune to the large conversion
errors that plague successive approximation converters
in high noise environments. Interfering signals with fre-
quency components at multiples of the averaging period
will be attenuated. Integrating ADCs commonly operate
with the signal integration period set to a multiple of the
50Hz/60Hz power line period (see Figure 3-2).
FIGURE 3-2:
NORMAL MODE
REJECTION OF DUAL
SLOPE CONVERTER
REF
Voltage
Analog
Input
Signal
Display
Switch
Driver
Control
Logic
Clock
Counter
Polarity Control
Phase
Control
VIN ≈ VREF
VIN ≈ 1.2 VREF
Variable
Reference
Integrate
Time
Fixed
Signal
Integrate
Time
Integrator
Comparator
Where:
VR = Reference voltage
TSI = Signal integration time (fixed)
TRI = Reference voltage integration time (variable)
1
RC
TSI
0
VIN(t)dt =
VRTRI
RC
V
IN
V
R
T
RI
T
SI
-------
=
30
20
10
0
0.1/t
1/t
10/t
Input Frequency
t = Measurement Period


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