Thermal Pad

(Bottom Side)

21

GND

EN

RT

SYNC

VIN

PVIN

PVIN

PGND

PGND

PGND

PH

PH

PH

PH

PH

BOOT

VSENSE

COMP

SS/TR

PWRGD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

TPS50301-HT, TPS50601-SP

SLVSA94H – DECEMBER 2012 – REVISED JULY 2015

www.ti.com

6 Pin Configuration and Functions

HKH Package

20-Pin CFP

Top View

Pin Functions

PIN

DESCRIPTION

NO.

NAME

1

GND

2

EN

Enable pin. Float to enable. Adjust the input undervoltage lockout (UVLO) with two resistors.

3

RT

In internal oscillation mode, a resistor is connected between the RT pin and GND to set the switching frequency.

4

SYNC

Optional 1-MHz external system clock input. The device operates with an internal oscillator if this pin is left open.

5

VIN

Supplies the power to the output FET controllers

6

PVIN

Power input. Supplies the power switches of the power converter

7

8

9

PGND

Return for low-side power MOSFET

10

11

12

13

PH

Switch node

14

15

A bootstrap capacitor is required between BOOT and PH. The voltage on this capacitor carries the gate drive voltage

16

BOOT

for the high-side MOSFET.

17

VSENSE

Inverting input of the gm error amplifier

18

COMP

Error amplifier output and input to the output switch current comparator. Connect frequency compensation to this pin.

Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time. The

19

SS/TR

voltage on this pin overrides the internal reference. It can be used for tracking and sequencing.

Power Good fault pin. Asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, or EN

20

PWRGD

shutdown, or during slow start.

(1)

Thermal pad (analog ground) must be connected to PGND external to the package.

4

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