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SN74LS163AM датащи(PDF) 5 Page - ON Semiconductor

номер детали SN74LS163AM
подробное описание детали  BCD Decade Counters 4?묪it Binary Counters
Download  8 Pages
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производитель  ONSEMI [ON Semiconductor]
домашняя страница  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

SN74LS163AM датащи(HTML) 5 Page - ON Semiconductor

  SN74LS163AM Datasheet HTML 1Page - ON Semiconductor SN74LS163AM Datasheet HTML 2Page - ON Semiconductor SN74LS163AM Datasheet HTML 3Page - ON Semiconductor SN74LS163AM Datasheet HTML 4Page - ON Semiconductor SN74LS163AM Datasheet HTML 5Page - ON Semiconductor SN74LS163AM Datasheet HTML 6Page - ON Semiconductor SN74LS163AM Datasheet HTML 7Page - ON Semiconductor SN74LS163AM Datasheet HTML 8Page - ON Semiconductor  
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SN74LS161A, SN74LS163A
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5
AC CHARACTERISTICS (TA = 25°C)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
fMAX
Maximum Clock Frequency
25
32
MHz
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL
Propagation Delay
Clock to TC
20
18
35
35
ns
tPLH
tPHL
Propagation Delay
Clock to Q
13
18
24
27
ns
tPLH
tPHL
Propagation Delay
CET to TC
9.0
9.0
14
14
ns
tPHL
MR or SR to Q
20
28
ns
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
tWCP
Clock Pulse Width Low
25
ns
VCC = 5.0 V
tW
MR or SR Pulse Width
20
ns
ts
Setup Time, other*
20
ns
ts
Setup Time PE or SR
25
ns
th
Hold Time, data
3
ns
th
Hold Time, other
0
ns
trec
Recovery Time MR to CP
15
ns
*CEP, CET, or DATA
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
AC WAVEFORMS
Figure 1. Clock to Output Delays, Count
Frequency, and Clock Pulse Width
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
CP
Q
tW(H)
tW(L)
trec
tPHL
tPHL
tPLH
Other conditions:
PE = MR (SR) = H
CEP = CET = H
Other conditions:
PE = L
P0 = P1 = P2 = P3 = H
tW
Q0 V Q1 V Q2 V Q3
MR
CP


Аналогичный номер детали - SN74LS163AM

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Аналогичное описание - SN74LS163AM

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