3

Package Pin Description

PACKAGE PIN#

PIN SYMBOL

FUNCTION

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Electrical Characteristics:

−40°C ≤ T

Shift Clock Frequency

2.0

MHz

SCLK High Time

175

ns

SCLK Low Time

175

ns

SO Rise Time

150

ns

SO Fall Time

150

ns

SO Delay Time

150

ns

SI Setup Time

75

ns

SI Hold Time

75

ns

CS Setup Time

0

ns

CS Hold Time

75

ns

16 Lead SO Wide

16 Lead PDIP

1

1

Negative output for SINE coil.

2

2

Positive output for SINE coil.

34

Analog supply. Nominally 13.5V.

4,5,12,13

3,13,14

Gnd

Ground.

6

6

SI

Serial data input. Data present at the rising edge of the

clock signal is shifted into the internal shift register.

77

5V logic supply. The internal registers and latches are

reset by a POR generated by the rising edge of the voltage

on this pin.

8

8

OE

Controls the state of the output buffers. A logic low on

this pin turns them off.

9

9

SCLK

Serial clock for shifting in/out of data. Rising edge shifts

data on SI into the shift register and the falling edge

changes the data on SO.

10

10

CS

When high allows data at SI to be shifted into part with

the rising edges of SCLK. The falling edge transfers the

shift register contents into the DAC and multiplexer to

update the output buffers. The falling edge also re-enables

the output drivers if they have been disabled by a fault.

11

11

ST

STATUS reflects the state of the outputs and is low any-

time the outputs are disabled, either by OE or the internal

protection circuitry. Requires external pull-up resistor.

14

5

SO

Serial data output. Existing 10-bit data is shifted out when

new data is shifted in. Allows cascading of multiple

devices on common serial port.

15

15

Negative output for COSINE coil.

16

16

Positive output for COSINE coil.

12

NC

No connection.