Si5320

6

Rev. 2.5

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Supply Current 1

Clock in = 622.08 MHz

Clock out = 19.44 MHz

—

141

155

mA

Supply Current 2

Clock in = 19.44 MHz

Clock out = 622.08 MHz

—

135

145

mA

Power Dissipation Using 3.3 V Supply

Clock Output

Clock in = 19.44 MHz

Clock out = 622.08 MHz

—

445

479

mW

(CLKIN)

1.0

1.5

2.0

V

(CLKIN)

See Figure 1A

200

—

(CLKIN)

See Figure 1B

200

—

Input Impedance

(CLKIN+, CLKIN–)

—80

—

k



Differential Output Voltage Swing

(CLKOUT)

100

 Load

Line-to-Line

816

906

1100

Output Common Mode Voltage

(CLKOUT)

100

 Load

Line-to-Line

1.4

1.8

2.2

V

Output Short to GND (CLKOUT)

–60

—

—

mA

—15

—

mA

Input Voltage Low (LVTTL Inputs)

——

0.8

V

Input Voltage High (LVTTL Inputs)

2.0

—

—

V

Input Low Current (LVTTL Inputs)

——

50

A

Input High Current (LVTTL Inputs)

——

50

A

Internal Pulldowns (All LVTTL Inputs)

——

50

A

Input Impedance (LVTTL Inputs)

50

—

—

k



Output Voltage Low (LVTTL Outputs)

—

—

0.4

V

Output Voltage High (LVTTL Outputs)

2.0

—

—

V

Notes:

1. The Si5320 device provides weak 1.5 V internal biasing that enables ac-coupled operation.

2. Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be ac

coupled to ground.

3. Transmission line termination, when required, must be provided externally.