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SI5369C-C-GQ датащи(PDF) 6 Page - Silicon Laboratories |
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SI5369C-C-GQ датащи(HTML) 6 Page - Silicon Laboratories |
6 / 84 page Si5369 6 Rev. 1.0 Output Clocks (CKOUTn)3,5,6 Common Mode CKOVCM LVPECL 100 load line-to-line VDD –1.42 — VDD –1.25 V Differential Output Swing CKOVD LVPECL 100 load line-to-line 1.1 — 1.9 VPP Single Ended Output Swing CKOVSE LVPECL 100 load line-to-line 0.5 — 0.93 VPP Differential Output Volt- age CKOVD CML 100 load line-to-line 350 425 500 mVPP Common Mode Output Voltage CKOVCM CML 100 load line-to-line —VDD–0.36 — V Differential Output Volt- age CKOVD LVDS 100 load line-to-line 500 700 900 mVPP Low Swing LVDS 100 load line-to-line 350 425 500 mVPP Common Mode Output Voltage CKOVCM LVDS 100 load line-to-line 1.125 1.2 1.275 V Differential Output Resistance CKORD CML, LVPECL, LVDS — 200 — Output Voltage Low CKOVOLLH CMOS — — 0.4 V Output Voltage High CKOVOHLH VDD =1.71V CMOS 0.8 x VDD —— V Table 2. DC Characteristics (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Current draw is independent of supply voltage 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD ≥ 2.5 V. 4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. 6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled. When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS. |
Аналогичный номер детали - SI5369C-C-GQ |
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Аналогичное описание - SI5369C-C-GQ |
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