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SI5369D-C-GQ датащи(PDF) 10 Page - Silicon Laboratories |
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SI5369D-C-GQ датащи(HTML) 10 Page - Silicon Laboratories |
10 / 84 page Si5369 10 Rev. 1.0 Output Rise/Fall (20–80%) @ 212.5 MHz output CKOTRF CMOS Output VDD =1.71 CLOAD =5 pF —— 8 ns Output Rise/Fall (20–80%) @ 212.5 MHz output CKOTRF CMOS Output VDD =2.97 CLOAD =5 pF —— 2 ns Output Duty Cycle Uncertainty @ 622.08 MHz CKODC 100 Load Line-to-Line Measured at 50% Point (Not for CMOS) —— ±40 ps LVCMOS Input Pins Minimum Reset Pulse Width tRSTMN 1— µs Reset to Microproces- sor Access Ready tREADY —— 10 ms Input Capacitance Cin —— 3 pF LVCMOS Output Pins Rise/Fall Times tRF CLOAD = 20pf See Figure 2 —25 — ns LOSn Trigger Window LOSTRIG From last CKINn to Internal detection of LOSn N3 ≠ 1 — — 4.5 x N3 TCKIN Time to Clear LOL after LOS Cleared tCLRLOL LOS to LOL Fold = Fnew Stable Xa/XB reference —10 — ms Device Skew Output Clock Skew tSKEW of CKOUTn to of CKOUT_m, CKOUTn and CKOUT_m at same frequency and signal format PHASEOFFSET =0 CKOUT_ALWAYS_ON =1 SQ_ICAL =1 —— 100 ps Table 3. AC Specifications (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Input to output phase skew after an ICAL is not controlled and can assume any value. 2. Lock and settle time performance is dependent on the frequency plan and the XAXB reference frequency. Please visit the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding the lock time of your frequency plan. |
Аналогичный номер детали - SI5369D-C-GQ |
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Аналогичное описание - SI5369D-C-GQ |
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