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SI53154 датащи(PDF) 6 Page - Silicon Laboratories |
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SI53154 датащи(HTML) 6 Page - Silicon Laboratories |
6 / 22 page Si53154 6 Rev. 1.1 Additive PCIe Gen 4 Phase Jitter RMSGEN4 PCIe Gen 4 — — 0.10 ps Additive Cycle to Cycle Jitter TCCJ Measured at 0 V differential — 20 50 ps Long-term Accuracy LACC Measured at 0 V differential — — 100 ppm Rising/Falling Slew rate TR/TF Measured differentially from ±150 mV 2.5 — 8 V/ns Crossing Point Voltage at 0.7 V Swing VOX 300 — 550 mV Enable/Disable and Setup Clock Stabilization from Power-Up TSTABLE —— 5 ms Stopclock Set-up Time TSS 10.0 — — ns Table 3. Absolute Maximum Conditions Parameter Symbol Condition Min Typ Max Unit Main Supply Voltage VDD_3.3V Functional — — 4.6 V Input Voltage VIN Relative to VSS –0.5 — 4.6 VDC Temperature, Storage TS Non-functional –65 — 150 °C Industrial Temperature, Operating Ambient TA Functional –40 — 85 °C Commercial Temperature, Operating Ambient TA Functional 0 — 85 °C Temperature, Junction TJ Functional — — 150 °C Dissipation, Junction to Case ØJC JEDEC (JESD 51) — — 35 °C/W Dissipation, Junction to Ambient ØJA JEDEC (JESD 51) — — 37 °C/W ESD Protection (Human Body Model) ESDHBM JEDEC (JESD 22 - A114) 2000 — – V Flammability Rating UL-94 UL (Class) V–0 Note: Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. Table 2. AC Electrical Specifications (Continued) Parameter Symbol Condition Min Typ Max Unit Notes: 1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. |
Аналогичный номер детали - SI53154 |
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Аналогичное описание - SI53154 |
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