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SI53313 датащи(PDF) 8 Page - Silicon Laboratories |
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SI53313 датащи(HTML) 8 Page - Silicon Laboratories |
8 / 33 page Si53313 8 Rev. 1.0 Figure 1. Differential Measurement Method Using a Balun Important: See AN925 for additional information on the dependence of measured additive jitter on the input source jitter. Table 11. Additive Jitter, Differential Clock Input VDD Input1,2 Output Additive Jitter (fs rms, 12 kHz to 20 MHz)3 Freq (MHz) Clock Format Amplitude VIN (Single-Ended, Peak-to-Peak) Differential 20%-80% Slew Rate (V/ns) Clock Format Typ Max 3.3 725 Differential 0.15 0.637 LVPECL 45 65 3.3 725 Differential 0.15 0.637 LVDS 50 65 3.3 156.25 Differential 0.5 0.458 LVPECL 160 185 3.3 156.25 Differential 0.5 0.458 LVDS 150 200 2.5 725 Differential 0.15 0.637 LVPECL 45 65 2.5 725 Differential 0.15 0.637 LVDS 50 65 2.5 156.25 Differential 0.5 0.458 LVPECL 145 185 2.5 156.25 Differential 0.5 0.458 LVDS 145 195 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. AC-coupled differential inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 2. PSPL 5310A CLKx CLKx 50 50 Balun 50 ohm AG E5052 Phase Noise Analyzer Si53313 DUT PSPL 5310A CLK SYNTH SMA103A Balun Low-Jitter Clock Source |
Аналогичный номер детали - SI53313 |
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Аналогичное описание - SI53313 |
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