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SI4700 датащи(PDF) 8 Page - Silicon Laboratories

номер детали SI4700
подробное описание детали  Device initialization sequence and busmode selection
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производитель  SILABS [Silicon Laboratories]
домашняя страница  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SI4700 датащи(HTML) 8 Page - Silicon Laboratories

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AN230
8
Rev. 0.9
2.2. 3-Wire Control Interface
For three-wire operation, a transfer begins when the SEN pin is set low on a rising SCLK edge. The control word is
latched internally on rising SCLK edges and is nine bits in length, comprised of a four bit chip address
A7:A4 = 0110b, a read/write bit (read = 1 and write = 0), and a four bit register address, A3:A0. The ordering of the
control word is A7:A5, R/W, A4:A0, as shown in Figure 4.
For write operations, the serial control word is followed by a 16-bit data word and is latched internally on rising
SCLK edges. The device does not latch the register write until the falling SCLK with SEN high.
Refer to “3-Wire Control Interface Characteristics” and “3-Wire Control Interface Write Timing Parameters” of the
device data sheet for more information.
Figure 4. 3-Wire Control Interface Write Timing Diagram
For read operations, a bus turn-around of half a cycle is followed by a 16-bit data word shifted out on rising SCLK
edges. The transfer ends on the rising SCLK edge after SEN is set high. Note that 26 SCLK cycles are required for
a transfer; however, SCLK may run continuously.
Refer to “3-Wire Control Interface Characteristics” and “3-Wire Control Interface Read Timing Parameters” of the
device data sheet for more information.
Figure 5. 3-Wire Control Interface Read Timing Diagram
A3
A2
A1
A0
D15
D14-D1
D0
A4
W
A5
A6
A7
Address + W = 01100xxxx
Data Out
SCLK
SDIO
SEN
26
th clock required
to latch the data.
A3
A2
A1
A0
D15
D14-D1
D0
A4
R
A5
A6
A7
Address + R = 01110xxxx
Data In
SCLK
SDIO
SEN
½ Cycle Bus
Turnaround
26
th clock required
to latch the data.


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