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STP7LN80K5 датащи(PDF) 4 Page - STMicroelectronics

номер детали STP7LN80K5
подробное описание детали  Ultra-low gate charge
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Electrical characteristics
STP7LN80K5
4/13
DocID028826 Rev 1
2
Electrical characteristics
TC = 25 °C unless otherwise specified
Table 5: On/off states
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V(BR)DSS
Drain-source breakdown
voltage
VGS = 0 V, ID = 1 mA
800
V
IDSS
Zero gate voltage drain
current
VGS = 0 V, VDS = 800 V
1
µA
VGS = 0 V, VDS = 800 V,
TC = 125 °C
50
µA
IGSS
Gate-body leakage current
VDS = 0 V, VGS = ±20 V
±10
µA
VGS(th)
Gate threshold voltage
VDS = VGS, ID =100 µA
3
4
5
V
RDS(on)
Static drain-source
on-resistance
VGS = 10 V, ID = 2.5 A
0.95
1.15
Ω
Table 6: Dynamic
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Ciss
Input capacitance
VDS= 100 V, f = 1 MHz,
VGS = 0 V
-
270
-
pF
Coss
Output capacitance
-
22
-
pF
Crss
Reverse transfer
capacitance
-
0.5
-
pF
Co(er)
(1)
Equivalent capacitance
energy related
VDS = 0 to 640 V, VGS = 0 V
-
17
-
nC
Co(tr)
(2)
Equivalent capacitance
time related
-
48
-
nC
RG
Intrinsic gate resistance
f = 1 MHz, ID=0 A
-
7.5
-
Ω
Qg
Total gate charge
VDD = 640 V, ID = 5 A, VGS = 10 V
(see Figure 15: "Test circuit for
gate charge behavior")
-
12
-
nC
Qgs
Gate-source charge
-
2.6
-
nC
Qgd
Gate-drain charge
-
8.6
-
nC
Notes:
(1)
Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS
increases from 0 to 80% VDSS
(2)
Time related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS
increases from 0 to 80% VDSS
Table 7: Switching times
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
td(on)
Turn-on delay time
VDD = 400 V, ID = 2.5 A,
RG = 4.7 Ω, VGS = 10 V (see Figure
14: "Test circuit for resistive load
switching times" and Figure 19:
"Switching time waveform")
-
9.3
-
ns
tr
Rise time
-
6.7
-
ns
td(off)
Turn-off-delay time
-
23.6
-
ns
tf
Fall time
-
17.4
-
ns


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