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DAC7563TDGSR датащи(PDF) 4 Page - Texas Instruments

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номер детали DAC7563TDGSR
подробное описание детали  Internal Reference
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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DAC7563TDGSR датащи(HTML) 4 Page - Texas Instruments

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SYNC
SCLK
D
IN
AV
DD
V
/V
REFIN
REFOUT
1
2
3
4
5
6
7
8
9
10
V
A
OUT
V
B
OUT
GND
LDAC
CLR
Thermal Pad
(1)
V
A
OUT
V
B
OUT
GND
LDAC
CLR
1
2
3
4
5
6
7
8
9
10
SYNC
SCLK
D
IN
AV
DD
V
/V
REFIN
REFOUT
DAC7562T, DAC7563T, DAC8162T
DAC8163T, DAC8562T, DAC8563T
SLASE61A – SEPTEMBER 2015 – REVISED OCTOBER 2015
www.ti.com
6 Pin Configuration and Functions
DGS Package
DSC Package
10-Pin VSSOP
10-Pin WSON
(Top View)
(Top View)
(1)
TI recommends connecting the thermal pad to the ground plane for better thermal dissipation.
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
AVDD
9
I
Power-supply input, 2.7 V to 5.5 V
Asynchronous clear input. The CLR input is falling-edge sensitive. On activation of CLR, zero
scale (DACxx62T) or mid-scale (DACxx63T) is loaded to all input and DAC registers. This sets the
CLR
5
I
DAC output voltages accordingly. The device exits clear code mode on the 24th falling edge of the
next write to the device. Activating CLR during a write sequence aborts the write.
Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the
DIN
8
I
serial clock input. Schmitt-trigger logic input
GND
3
Ground reference point for all circuitry on the device
In synchronous mode, data update occurs with the falling edge of the 24th SCLK cycle, which
follows a falling edge of SYNC. Such synchronous updates do not require the LDAC, which must
be connected to GND permanently or asserted and held low before sending commands to the
device.
LDAC
4
I
In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for
simultaneous DAC updates. Multiple single-channel commands can be written in order to set
different channel buffers to desired values and then make a falling edge on the LDAC pin to
update the DAC output registers simultaneously.
SCLK
7
I
Serial clock input. Data can be transferred at rates up to 50 MHz. Schmitt-trigger logic input
Level-triggered control input (active-low). This input is the frame synchronization signal for the
input data. When SYNC goes low, it enables the input shift register, and data are sampled on
subsequent falling clock edges. The DAC output updates following the 24th clock falling edge. If
SYNC
6
I
SYNC is taken high before the 23rd clock edge, the rising edge of SYNC acts as an interrupt, and
the write sequence is ignored by the DAC756xT, DAC816xT, and DAC856xT devices. Schmitt-
trigger logic input
VOUTA
1
O
Analog output voltage from DAC-A
VOUTB
2
O
Analog output voltage from DAC-B
VREFIN/VREFOUT
10
I/O
Bidirectional voltage reference pin. If internal reference is used, 2.5-V output.
4
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Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: DAC7562T DAC7563T DAC8162T DAC8163T DAC8562T DAC8563T


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