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SN74LV240ADBLE датащи(PDF) 4 Page - Texas Instruments |
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SN74LV240ADBLE датащи(HTML) 4 Page - Texas Instruments |
4 / 27 page SN54LV240A, SN74LV240A SCLS384I – SEPTEMBER 1997 – REVISED FEBRUARY 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature (unless otherwise noted) MIN MAX UNIT VCC Supply voltage –0.5 7 V VI Input voltage(2) –0.5 7 V VO Voltage applied to any output in the high-impedance or power-off state(2) –0.5 7 V VO Output voltage(2) (3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current VO = 0 to VCC –35 35 mA Continuous current through VCC or GND –70 70 mA Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The value is limited to 5.5-V maximum. 7.2 ESD Ratings VALUE UNIT Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Electrostatic V(ESD) Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 V discharge Machine model (A115-A) 200 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 4 Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: SN54LV240A SN74LV240A |
Аналогичный номер детали - SN74LV240ADBLE |
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Аналогичное описание - SN74LV240ADBLE |
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