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54F273DM датащи(PDF) 2 Page - National Semiconductor (TI) |
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54F273DM датащи(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Connection Diagrams Pin Assignment for DIP SOIC and Flatpak TLF9511 – 1 Pin Assignment for LCC TLF9511 – 2 Unit LoadingFan Out 54F74F Pin Names Description UL Input IIH IIL HIGHLOW Output IOH IOL D0–D7 Data Inputs 1010 20 mA b06 mA MR Master Reset (Active LOW) 1010 20 mA b06 mA CP Clock Pulse Input (Active Rising Edge) 1010 20 mA b06 mA Q0–Q7 Data Outputs 50333 b 1 mA20 mA Mode Select-Function Table Operating Mode Inputs Output MR CP Dn Qn Reset (Clear) L X X L Load ‘1’ H L hH Load ‘0’ H L lL H e HIGH Voltage Level steady state h e HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L e LOW Voltage Level steady state I e LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X e Immaterial L e LOW-to-HIGH clock transition Logic Diagram TLF9511 – 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2 |
Аналогичный номер детали - 54F273DM |
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Аналогичное описание - 54F273DM |
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