Unit LoadingFan Out

54F74F

Pin Names

Description

UL

E

Enable Input (Active LOW)

1010

Data Inputs

1010

CP

Clock Pulse Input (Active Rising Edge)

1010

Flip-Flop Outputs

50333

b

1 mA20 mA

Complement Outputs

50333

b

1 mA20 mA

Functional Description

The ’F379 consists of four edge-triggered D-Type flip-flops

with individual D inputs and Q and Q outputs The Clock

(CP) and Enable (E) inputs are common to all flip-flops

When the E is input HIGH the register will retain the present

change when the clock is in either state provided that the

recommended setup and hold times are observed

Truth Table

Inputs

Outputs

E

CP

H

L

XNC

NC

L

L

HH

L

L

L

LL

H

Logic Diagram

TLF9527 – 4

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays

2