Connection Diagrams

Pin Assignment

for DIP SOIC and Flatpak

TLF9469 – 1

Pin Assignment

for LCC

TLF9469 – 2

Unit LoadingFan Out

54F74F

Pin Names

Description

UL

HIGHLOW

Data Inputs

1010

Clock Pulse Inputs (Active Rising Edge)

1010

Direct Clear Inputs (Active LOW)

1030

Direct Set Inputs (Active LOW)

1030

Outputs

50333

b

1 mA20 mA

Truth Table

Inputs

Outputs

CP

D

Q

Q

LH

X

X

H

L

HL

X

X

L

H

LL

X

X

H

H

HH

L

hH

L

HH

L

lL

H

HH

L

X

Lower case letters indicate the state of the referenced input or output one

setup time prior to the LOW-to-HIGH clock transition

Logic Diagram

TLF9469 – 5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays

2