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AD6674-750EBZ датащи(PDF) 4 Page - Analog Devices |
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AD6674-750EBZ датащи(HTML) 4 Page - Analog Devices |
4 / 91 page AD6674 Data Sheet The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and up to four half-band decimation filters. Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6674 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining a 9-bit output resolution. NSR is enabled by default on the AD6674. Each ADC output is also connected internally to a VDR block. This optional mode allows full dynamic range for defined input signals. Inputs that are within a defined mask (based on DPD applications) are passed unaltered. Inputs that violate this defined mask result in the reduction of the output resolution. With VDR, the dynamic range of the observation receiver is determined by a defined input frequency mask. For signals falling within the mask, the outputs are presented at the maximum resolution allowed. For signals exceeding defined power levels within this frequency mask, the output resolution is truncated. This mask is based on DPD applications and supports tunable real IF sampling, and zero IF or complex IF receive architectures. Operation of the AD6674 between the DDC, NSR, and VDR modes is selectable via SPI-programmable profiles. In addition to the DDC blocks, the AD6674 has several functions that simplify the AGC function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. Besides the fast detect outputs, the AD6674 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC. Users can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of two-lane and four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins. The AD6674 has flexible power-down options that allow signifi- cant power savings when desired. All of these features can be programmed using a 1.8 V capable 3-wire serial port interface (SPI). The AD6674 is available in a Pb-free, 64-lead LFCSP, specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. Wide full power bandwidth supports IF sampling of signals up to 2 GHz. 2. Buffered inputs with programmable input termination eases filter design and implementation. 3. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. 4. Flexible SPI controls various product features and functions to meet specific system requirements. 5. Programmable fast overrange detection and signal monitoring. 6. Programmable fast overrange detection. 7. 9 mm × 9 mm 64-lead LFCSP. Rev. B | Page 4 of 91 |
Аналогичный номер детали - AD6674-750EBZ |
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Аналогичное описание - AD6674-750EBZ |
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