поискавой системы для электроныых деталей |
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UC1875-SP датащи(PDF) 3 Page - Texas Instruments |
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UC1875-SP датащи(HTML) 3 Page - Texas Instruments |
3 / 36 page 20 19 21 17 15 18 23 22 24 14 13 16 5 6 4 8 10 7 2 3 1 11 12 9 N/C VREF EA- N/C EA+ CLOCKSYNC E / AOUT OUTB CS+ PWRGND OUTA OUTC SOFTSTART OUTD VC DELAYSET C-D VIN DELAYSET A-B RAMP FRQSET GND SLOPE N/C N/C 4 25 24 23 OUTA 2 3 1 28 22 21 5 6 7 8 9 12 14 13 15 16 N/C N/C OUTC OUTD N/C DELAYSET C-D SS CS+ EA+ DELAYSET A-B FREQSET CLOCKSYNC SLOPE RAMP E/A- N/C N/C N/C GND 10 11 17 18 20 19 27 26 OUTB PWRGND VIN N/C E/A OUT VREF N/C VC UC1875-SP www.ti.com SLUSAQ9B – DECEMBER 2011 – REVISED DECEMBER 2015 5 Description (continued) Protective features include an undervoltage lockout which maintains all outputs in an active-low state until the supply reaches a 10.75-V threshold. 1.5 hysteresis is built in for reliable, boot-strapped chip supply. Overcurrent protection is provided, and will latch the outputs in the OFF state within 70 ns of a fault. The current-fault circuitry implements full-cycle restart operation. Additional features include an error amplifier with bandwidth in excess of 7 MHz, a 5-V reference, provisions for soft-starting, and flexible ramp generation and slope compensation circuitry. This device is available in hermetically sealed cerdip, surface mount, and ceramic leadless chip carrier packages for –55°C to 125°C operation. 6 Pin Configuration and Functions J Package FK Package 20-Pin CDIP 28-Pin LCCC Top View Top View W Package 24-Pin CFP Top View Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: UC1875-SP |
Аналогичный номер детали - UC1875-SP_15 |
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Аналогичное описание - UC1875-SP_15 |
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