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UC1875-SP датащи(PDF) 5 Page - Texas Instruments

номер детали UC1875-SP
подробное описание детали  Rad-Tolerant Class-V, Phase Shift Resonant Controller
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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UC1875-SP датащи(HTML) 5 Page - Texas Instruments

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UC1875-SP
www.ti.com
SLUSAQ9B – DECEMBER 2011 – REVISED DECEMBER 2015
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
CDIP
LCCC
CFP
Voltage ramp. This pin is the input to the pulse width modulator
comparator. Connect a capacitor from here to GND. A voltage ramp is
RAMP
19
11
22
I
developed at this pin with a slope: (dV/dT) = (sense voltage/RSLOPE ×
CRAMP).
Set ramp slope compensation. A resistor from this pin to VCC will set
SLOPE
18
10
21
I
the current used to generate the ramp. Connecting this resistor to the
DC input line will provide voltage feed forward.
SOFT START will remain at GND as long as VIN is below the UVLO
threshold. SOFT START will be pulled up to about 4.8 V by an internal
9
μA current source when VIN becomes valid (assuming a non-fault
condition). In the event of a current-fault (C/S (+) voltage exceeding
SOFT-
2.5 V), SOFT START will be pulled to GND and then ramp to 4.8 V. If
6
23
7
O
START
a fault occurs during the SOFT START cycle, the outputs will be
immediately disabled and SOFT START must charge fully prior to
resetting the fault latch. For paralleled controllers, the SOFT START
pins may be paralleled to a single capacitor, but the change currents
will be additive.
Output switch supply voltage. This pin supplies power to the drivers
and their associated bias circuitry. Connect VC to a stable source
VC
10
28
11
I
above 3 V for normal operation, above 12 V for best performance.
This supply should be bypassed directly to the PWR GND pin with low
ESR, low ESL capacitors.
Primary chip supply voltage. This pin supplies power to the logic and
VIN
11
1
14
I
analog circuitry on the integrated circuitry that is not directly
associated with driving the output stages.
This pin is an accurate 5 V voltage reference. This output is capable
VREF
1
16
2
I
of delivering about 60 mA to peripheral circuitry and is internally short
circuit current limited.
Table 1. Under Voltage Threshold (UVLO)
UVLO TURN-ON
UVLO TURN-OFF
DELAY SET
UCC1875-SP
10.75V
9.25V
Yes
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
UNIT
Supply voltage (VC, VIN)
20
V
DC
0.5
A
Output current, source or sink
Pulse (0.5 µs)
3
A
Analog inputs
(Pins 1, 2, 3, 4, 5, 6, 7, 15, 16, 17, 18, 19)
–0.3
5.3
V
Maximum junction temperature, JTmax
150
J package
7
Thermal Resistance, RθJC(top)
W package
5.4
°C/W
FK package
5.6
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
Pin references are to 20-pin packages. All voltages are with respect to ground. Currents are positive into, negative out of the device
terminals.
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
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