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UC1875-SP датащи(PDF) 10 Page - Texas Instruments

номер детали UC1875-SP
подробное описание детали  Rad-Tolerant Class-V, Phase Shift Resonant Controller
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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UC1875-SP датащи(HTML) 10 Page - Texas Instruments

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UC1875-SP
SLUSAQ9B – DECEMBER 2011 – REVISED DECEMBER 2015
www.ti.com
8 Detailed Description
8.1 Overview
Using the conventional full-bridge topology with phase-shifted control technique has already demonstrated its
superiority in medium to high power, DC-to-DC power conversion. This control method provides well controlled
dv/dt values and zero-voltage switching of all primary side semiconductors in the power stage over nearly all
operating conditions. The major benefits offered by this approach are a simpler power stage than its hard
switched counterpart, utilizing circuit parasitics instead of being penalized by them, improved efficiency and lower
EMI level. These significant advantages are realized with a slightly more complex control algorithm.
The UC1875-SP implements control of a bridge power stage by phase-shifting the switching of one half-bridge
with respect to the other, allowing constant frequency pulse-width modulation in combination with resonant, zero-
voltage switching for high efficiency performance at high frequencies. This circuit may be configured to provide
control in either voltage or current-mode operation, with a separate overcurrent shutdown for fast fault protection.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 CLKSYNC
(Bidirectional clock and synchronization pin): Used as an output, this pin provides a clock signal. As an input, this
pin provides a synchronization point. In its simplest usage, multiple devices, each with their own local oscillator
frequency, may be connected together by the CLOCKSYNC pin and will synchronize on the fastest oscillator.
This pin may also be used to synchronize the device to an external clock, provided the external signal is of
higher frequency than the local oscillator. A resistor load may be needed on this pin to minimize the clock pulse
width.
8.3.2 E/AOUT
(Error Amplifier Output): This is is the gain stage for overall feedback control. Error amplifier output voltage levels
below 1 volt will force 0° phase shift. Since the error amplifier has a relatively low current drive capability, the
output may be overridden by driving with a sufficiently low impedance source.
10
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