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UC1875-SP датащи(PDF) 11 Page - Texas Instruments

номер детали UC1875-SP
подробное описание детали  Rad-Tolerant Class-V, Phase Shift Resonant Controller
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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UC1875-SP датащи(HTML) 11 Page - Texas Instruments

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(RAMP)
(SLOPE)
dV
Sense Voltage
=
dT
R
x C
UC1875-SP
www.ti.com
SLUSAQ9B – DECEMBER 2011 – REVISED DECEMBER 2015
Feature Description (continued)
8.3.3 CS+
(Current Sense): The non-inverting input to the current-fault comparator whose reference is set internally to a
fixed 2.5 V (separate from VREF). When the voltage at this pin exceeds 2.5 V the current-fault latch is set, the
outputs are forced OFF and a SOFT-START cycle is initiated. If a constant voltage above 2.5 V is applied to this
pin the outputs are disabled from switching and held in a low state until the CS+ pin is brought below 2.5 V. The
outputs may begin switching at 0 degrees phase shift before the SOFTSTART pin begins to rise -- this condition
will not prematurely deliver power to the load.
8.3.4 FREQSET
(Oscillator Frequency Set pin): A resistor and a capacitor from FREQSET to GND will set the oscillator
frequency.
8.3.5 DELSETA-B, DELSETC-D
(Output Delay Control): The user programmed current flowing from these pins to GND set the turn-on delay for
the corresponding output pair. This delay is introduced between turn-off of one switch and turn-on of another in
the same leg of the bridge to provide a dead time in which the resonant switching of the external power switches
takes place. Separate delays are provided for the two half-bridges to accommodate differences in the resonant
capacitor charging currents.
8.3.6 EA–
(Error Amplifier Inverting Input): This is normally connected to the voltage divider resistors which sense the
power supply output voltage level.
8.3.7 EA+
(Error Amplifier Non-Inverting Input): This is normally connected to a reference voltage used for comparison with
the sensed power supply output voltage level at the EA+ pin.
8.3.8 GND
(Signal Ground): All voltages are measured with respect to GND. The timing capacitor, on the FREQSET pin,
any bypass capacitor on the VREF pin, bypass capacitors on VIN and the ramp capacitor, on the RAMP pin,
should be connected directly to the ground plane near the signal ground pin.
8.3.9 OUTA – OUTD
(Outputs A-D): The outputs are 2 A totem-pole drivers optimized for both MOSFET gates and level-shifting
transformers. The outputs operate as pairs with a nominal 50% duty-cycle. The A-B pair is intended to drive one
half-bridge in the external power stage and is syncronized with the clock waveform. The C-D pair will drive the
other half-bridge with switching phase shifted with respect to the A-B outputs.
8.3.10 PWRGND
(Power Ground): VC should be bypassed with a ceramic capacitor from the VC pin to the section of the ground
plane that is connected to PWRGND. Any required bulk reservoir capacitor should parallel this one. Power
ground and signal ground may be joined at a single point to optimize noise rejection and minimize DC drops.
8.3.11 RAMP
(Voltage Ramp): This pin is the input to the PWM comparator. Connect a capacitor from here to GND. A voltage
ramp is developed at this pin with a slope:
Current mode control may be achieved with a minimum amount of external circuitry, in which case this pin
provides slope compensation.
Copyright © 2011–2015, Texas Instruments Incorporated
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