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ADC0841CCN датащи(PDF) 3 Page - National Semiconductor (TI) |
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ADC0841CCN датащи(HTML) 3 Page - National Semiconductor (TI) |
3 / 16 page Electrical Characteristics (Continued) The following specifications apply for V CC=5VDC unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits T A=Tj=25˚C. ADC0841BCN, ADC0841CCN ADC0841BCV, ADC0841CCV Symbol Parameter Conditions Typ Tested Design Units (Note 6) Limit Limit (Note 7) (Note 8) DIGITAL AND DC CHARACTERISTICS I IN(0) Logical “0” Input V IN=0V −0.005 −1 µA Current (Max) V OUT(1) Logical “1” V CC=4.75V Output Voltage (Min) I OUT=−360 µA 2.8 2.4 V I OUT=−10 µA 4.6 4.5 V V OUT(0) Logical “0” V CC=4.75V 0.34 0.4 V Output Voltage (Max) I OUT=1.6 mA I OUT TRI-STATE Output V OUT=0V −0.01 −0.3 −3 µA Current (Max) V OUT=5V 0.01 0.3 3 µA I SOURCE Output Source V OUT=0V −14 −7.5 −6.5 mA Current (Min) I SINK Output Sink V OUT=VCC 16 9.0 8.0 mA Current (Min) I CC Supply Current (Max) CS =1, V REF Open 1 2.3 2.5 mA AC Characteristics The following specifications apply for V CC = 5VDC,tr = tf = 10 ns unless otherwise specified. Boldface limits apply from TMIN to T MAX; all other limits TA = TJ = 25˚C. Tested Design Symbol Parameter Conditions Typ Limit Limit Units (Note 6) (Note 7) (Note 8) t C Maximum Conversion Time (See Graph) 30 40 60 µs t W(WR) Minimum WR Pulse Width (Note 9) 50 150 ns t ACC Maximum Access Time (Delay from Falling Edge C L = 100 pF 145 225 ns of RD to Output Data Valid) (Note 9) t 1H,t0H TRI-STATE Control (Maximum Delay from Rising C L = 10 pF, RL = 10k, 125 200 ns Edge of RD to Hi-Z State) t r = 20 ns (Note 9) t WI,tRI Maximum Delay from Falling Edge of WR or RD to (Note 9) 200 400 ns Reset of INTR C IN Capacitance of Logic Inputs 5 pF C OUT Capacitance of Logic Outputs 5 pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to the ground pins. Note 3: During over-voltage conditions (VIN<0V and VIN>VCC) the maximum input current at any one pin is ±5 mA. If the current is limited to ±5 mA at all the pins no more than four pins can be in this condition in order to meet the Input Current Per Package (±20 mA) specification. Note 4: Total unadjusted error includes offset, full-scale, and linearity. Note 5: For VIN (−) ≥ VIN (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input, which will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply. Be careful during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to5VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 6: Typicals are at 25˚C and represent most likely parametric norm. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Design limits are guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels. Note 9: The temperature coefficient is 0.3%/˚C. Note 10: Human body model, 100 pF discharged through 1.5 k Ω resistor. www.national.com 3 |
Аналогичный номер детали - ADC0841CCN |
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Аналогичное описание - ADC0841CCN |
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