поискавой системы для электроныых деталей |
|
ADCV0831 датащи(PDF) 6 Page - National Semiconductor (TI) |
|
|
ADCV0831 датащи(HTML) 6 Page - National Semiconductor (TI) |
6 / 9 page Functional Description The design of this converter utilizes a comparator structure with built-in sample-and-hold which provides for V IN to be converted by a successive approximation routine. The analog input voltage can range from 50mV below ground to 50mV above V CC without degrading conversion accuracy. The ADCV0831 is intended to work with a CPU which strobes data on the clock’s rising edge. The ADCV0831 strobes data on the clock’s falling edge so that the data out- put is stable when the CPU reads it in. When the Chip Select pin is high, the output is TRI-STATE and the ADCV0831 is in shutdown mode and draws less than 30 µA of current. During shutdown the digital logic draws no current at CMOS logic levels, and the analog cir- cuitry is turned off. When the Chip Select pin goes low, all the analog circuitry turns on, and the conversion process begins. 1.0 THE DIGITAL INTERFACE The most important characteristic of this converter is the se- rial data link with the controlling processor. Using a serial communication format offers three very significant system improvements. It allows many functions to be included in a small package, it can eliminate the transmission of low level analog signals by locating the converter right at the analog sensor, and can transmit highly noise immune digital data back to the host processor. To understand the operation of this converter it is best to re- fer to the Timing Diagrams and to follow a complete conver- sion sequence. 1. A conversion is initiated by pulling the CS (chip select) line low. This line must be held low for the entire conver- sion. 2. During the conversion the output of the SAR comparator indicates whether the analog input is greater than (high) or less than (low) a series of successive voltages in a re- sistor ladder (last 8 bits). After each comparison the comparator’s output is shifted to the DO line on the fall- ing edge of CLK. This data is the result of the conversion being shifted out (with the MSB first) and can be read by the processor immediately. 3. After 11 clock periods the conversion is completed. 4. All internal registers are cleared when the CS line is high. See Data Input Timing under Timing Diagrams. If another conversion is desired CS must make a high to low transition. 2.0 REFERENCE CONSIDERATIONS In a ratiometric system, the analog input voltage is propor- tional to the voltage used for the A/D reference. This voltage is the system power supply. This technique relaxes the sta- bility requirements of the system reference as the analog in- put and A/D reference move together maintaining the same output code for a given input condition. Since there is no separate reference and analog supply pins, the analog side is very sensitive. The PC layout of the ADCV0831 is very critical. The ADCV0831 should be used with an analog ground plane and single-point grounding techniques. The Gnd pin should be tied directly to the ground plane. One supply bypass capacitor (0.1 µF) is recom- mended to decouple all the digital signals on the supplies. The lead length of the capacitor should be as short as pos- sible. 3.0 THE ANALOG INPUT The most important feature of this converter is that it can be located right at the analog signal source through just a few wires. It can communicate with a processor with a highly noise immune serial bit stream. This greatly minimizes cir- cuitry to maintain analog signal accuracy which otherwise is most susceptible to noise pickup. However, a few words are in order with regard to the analog inputs should the input be noisy to begin with or possibly riding on a large common-mode voltage. The input has a sample and hold, therefore a capacitor (0.01 µF) is needed at the input pin in order to swamp out any feedthrough signal coming from the sample and hold cir- cuitry. The input capacitor lead length is not as critical as the supply decoupling capacitor, as long as the capacitor is large enough to swamp out any sample and hold feedthrough. Source resistance limitation is important with regard to the DC leakage currents of the input multiplexer. Bypass capaci- tors should not be used if the source resistance is greater than 1k Ω. The worst-case leakage current of ±1µA over tem- perature will create a 1mV input error with a 1k Ω source re- sistance. An op-amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance signal source be required. DS100104-59 Recommended Power Supply Bypassing www.national.com 6 |
Аналогичный номер детали - ADCV0831 |
|
Аналогичное описание - ADCV0831 |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |