FM25640-S datasheet(3/14 Pages) RAMTRON

номер детали	FM25640-S

подробное описание детали	64Kb FRAM Serial Memory

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производитель	RAMTRON [Ramtron International Corporation]

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FM25640

Rev. 2.1

Aug 2003

3 of 14

Overview

The FM25640 is a serial FRAM memory. The

memory array is logically organized as 8,192 x 8 and

is accessed

using an industry standard Serial

Peripheral Interface or SPI bus. Functional operation

of the FRAM is similar to serial EEPROMs. The

major difference between the FM25640 and a serial

EEPROM with the same pin-out relates to its

superior write performance.

Memory Architecture

When accessing the FM25640, the user addresses

8,192 locations each with 8 data bits. These data bits

are shifted serially. The addresses are accessed using

the SPI protocol, which includes a chip select (to

permit multiple devices on the bus), an op-code and a

two-byte address. The upper 3 bits of the address

range are ‘don’t care’ values. The complete address

of 13-bits specifies each byte address uniquely.

Most functions of the FM25640 either are controlled

by the SPI interface or are handled automatically by

on-board circuitry. The access time for memory

operation essentially is zero, beyond the time needed

for the serial protocol. That is, the memory is read or

written at the speed of the SPI bus. Unlike an

EEPROM, it is not necessary to poll the device for a

ready condition since writes occur at bus speed. That

is, by the time a new bus transaction can be shifted

into the part, a write operation will be complete. This

is explained in more detail in the interface section

below.

Users expect several obvious system benefits from

the FM25640 due to its fast write cycle and high

endurance as compared with EEPROM. However

there are less obvious benefits as well. For example

in a high noise environment, the fast-write operation

is less susceptible to corruption than an EEPROM

since it is completed quickly. By contrast, an

EEPROM

requiring

milliseconds

to

write

is

vulnerable to noise during much of the cycle.

Note

that

the

FM25640

contains

no

power

management circuits other than a simple internal

power-on reset. It is the user’s responsibility to

ensure that VDD is within data sheet tolerances to

prevent incorrect operation.

Serial Peripheral Interface – SPI Bus

The FM25640 employs a Serial Peripheral Interface

(SPI) bus. It is specified to operate at speeds up to 5

MHz. This high-speed serial bus provides high

performance

serial

communication

to

a

host

microcontroller.

Many common

microcontrollers

have hardware SPI ports allowing a direct interface.

It is quite simple to emulate the port using ordinary

port pins for microcontrollers that do not. The

FM25640 operates in SPI Mode 0 and 3.

The SPI interface uses a total of four pins: clock,

data-in, data-out, and chip select. It is possible to

connect the two data lines together. Figure 2

illustrates a typical system configuration using the

FM25640 with a microcontroller that offers an SPI

port. Figure 3 shows a similar configuration for a

microcontroller that has no hardware support for the

SPI bus.

Protocol Overview

The SPI interface is a synchronous serial interface

using clock and data lines. It is intended to support

multiple devices on the bus. Each device is activated

using a chip select. Once chip select is activated by

the bus master, the FM25640 will begin monitoring

the clock and data lines. The relationship between the

falling edge of /CS, the clock and data is dictated by

the SPI mode. The device will make a determination

of the SPI mode on the falling edge of each chip

select. While there are four such modes, the

FM25640 supports modes 0 and 3. Figure 4 shows

the required signal relationships for modes 0 and 3.

For both modes, data is clocked into the FM25640 on

the rising edge of SCK and data is expected on the

first rising edge after /CS goes active. If the clock

begins from a high state, it will fall prior to beginning

data transfer in order to create the first rising edge.

The SPI protocol is controlled by op-codes. These

op-codes specify the commands to the part. After /CS

is activated the first byte transferred from the bus

master is the op-code. Following the op-code, any

addresses and data are then transferred.

Certain op-codes are commands with no subsequent

data transfer. The /CS must go inactive after an

operation is complete and before a new op-code can

be issued. There is one valid op-code only per active

chip select.

Аналогичный номер детали - FM25640-S

производитель	номер детали	датащи	подробное описание детали
Ramtron International C...	FM25640-S	187Kb / 13P	64Kb FRAM Serial Memory

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Аналогичное описание - FM25640-S

производитель	номер детали	датащи	подробное описание детали
Ramtron International C...	FM25640	187Kb / 13P	64Kb FRAM Serial Memory
	FM24C64	98Kb / 12P	64Kb FRAM Serial Memory
	FM25640	138Kb / 13P	64Kb FRAM Serial Memory
	FM25CL64	131Kb / 13P	64Kb FRAM Serial 3V Memory
	FM24CL64	115Kb / 13P	64Kb Serial 3V FRAM Memory
	FM25CL64	137Kb / 13P	64Kb FRAM Serial 3V Memory
List of Unclassifed Man...	FM24CL64	96Kb / 13P	64Kb 2.7V-3.6V FRAM Serial Memory
Ramtron International C...	FM1608	104Kb / 12P	64Kb Bytewide FRAM Memory
Ramtron International C...	FM24CL04	116Kb / 11P	4Kb FRAM Serial Memory
List of Unclassifed Man...	FM25C160	154Kb / 14P	16Kb FRAM Serial Memory

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