OBSOLETE

54AC257, 54ACT257

www.ti.com

SNOS102B – JULY 1998 – REVISED APRIL 2013

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Copyright © 1998–2013, Texas Instruments Incorporated

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