ADC081500 datasheet(11/47 Pages) TI1

номер детали	ADC081500

подробное описание детали	High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter

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ADC081500

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SNAS319G – JUNE 2005 – REVISED APRIL 2013

Converter Electrical Characteristics (continued)

The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN (a.c. coupled) Full Scale Range =

differential 870mVP-P, CL = 10 pF, Differential (a.c. coupled) sinewave input clock, fCLK = 1.5 GHz at 0.5VP-P with 50% duty

cycle, VBG = Floating, Normal Control Mode, Single Data Rate Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance

= 100

Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted.

(1)(2)

Units

Symbol

Parameter

Conditions

Typical(3)

Limits(3)

(Limits)

TEMPERATURE DIODE CHARACTERISTICS

192 µA vs. 12 µA,

71.23

mV

TJ = 25°C

ΔVBE

Temperature Diode Voltage

192 µA vs. 12 µA,

85.54

mV

TJ = 85°C

CLOCK INPUT CHARACTERISTICS

0.4

VP-P (min)

Sine Wave Clock

0.6

2.0

VP-P (max)

VID

Differential Clock Input Level

0.4

VP-P (min)

Square Wave Clock

0.6

2.0

VP-P (max)

II

Input Current

VIN = 0 or VIN = VA

±1

µA

Differential

0.02

pF

CIN

Input Capacitance (7) (8)

Each input to ground

1.5

pF

DIGITAL CONTROL PIN CHARACTERISTICS

VIH

Logic High Input Voltage

See (9)

0.85 x VA

V (min)

VIL

Logic Low Input Voltage

See (9)

0.15 x VA

V (max)

CIN

Input Capacitance (8) (10)

Each input to ground

1.2

pF

DIGITAL OUTPUT CHARACTERISTICS

400

mVP-P (min)

Measured differentially, OutV = VA,

710

VBG = Floating

(11)

920

mVP-P (max)

VOD

LVDS Differential Output Voltage

280

mVP-P (min)

Measured differentially, OutV =

510

GND, VBG = Floating

(11)

720

mVP-P (max)

Change in LVDS Output Swing

Δ VO DIFF

±1

mV

Between Logic Levels

VOS

Output Offset Voltage

VBG = Floating

800

mV

VOS

Output Offset Voltage

VBG = VA

(11)

1200

mV

Output Offset Voltage Change

Δ VOS

±1

mV

Between Logic Levels

Output+ & Output- connected to

IOS

Output Short Circuit Current

±4

mA

0.8V

ZO

Differential Output Impedance

100

Ohms

VOH

CalRun High level output

IOH = -400uA

(9)

1.65

1.5

V

VOL

CalRun Low level output

IOH = 400uA

(9)

0.15

0.3

V

(7)

The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF

each pin to ground are isolated from the die capacitances by lead and bond wire inductances.

(8)

This parameter is specified by design and is not tested in production.

(9)

This parameter is specified by design and/or characterization and is not tested in production.

(10) The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated

from the die capacitances by lead and bond wire inductances.

(11) Tying VBG to the supply rail will increase the output offset voltage (VOS) by 400mv (typical), as shown in the VOS specification above.

Tying VBG to the supply rail will also affect the differential LVDS output voltage (VOD), causing it to increase by 40mV (typical).

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Аналогичный номер детали - ADC081500

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