поискавой системы для электроныых деталей |
|
74LVC1G373DBVRE4 датащи(PDF) 1 Page - Texas Instruments |
|
|
74LVC1G373DBVRE4 датащи(HTML) 1 Page - Texas Instruments |
1 / 20 page Seemechanicaldrawingsfordimensions. DBVPACKAGE (TOP VIEW) DCKPACKAGE (TOP VIEW) 2 GND V CC 5 3 4 D Q 6 1 LE OE 3 4 D 2 GND Q 5 1 LE V CC 6 OE YZP PACKAGE (BOTTOMVIEW) 2 GND V CC 1 5 LE D 4 3 Q 6 OE SN74LVC1G373 www.ti.com SCES528D – DECEMBER 2003 – REVISED DECEMBER 2013 Single D-Type Latch With 3-State Output Check for Samples: SN74LVC1G373 While the latch-enable (LE) input is high, the Q output 1 FEATURES follows the data (D) input. When LE is taken low, the 2 • Available in the Texas Instruments NanoFree™ Q output is latched at the logic level set up at the D Package input. • Supports 5-V VCC Operation NanoFree™ package technology is a major • Inputs Accept Voltages to 5.5 V breakthrough in IC packaging concepts, using the die as the package. • Provides Down Translation to VCC • Max tpd of 4 ns at 3.3 V OE does not affect the internal operations of the latch. Old data can be retained or new data can be • Low Power Consumption, 10- μA Max ICC entered while the outputs are in the high-impedance • ±24-mA Output Drive at 3.3 V state. • Ioff Supports Live Insertion, Partial-Power- A buffered output-enable (OE) input can be used to Down Mode, and Back Drive Protection place the output in either a normal logic state (high or • Latch-Up Performance Exceeds 100 mA Per low logic levels) or the high-impedance state. In the JESD 78, Class II high-impedance state, the output neither loads nor • ESD Protection Exceeds JESD 22 drives the bus lines significantly. The high-impedance state and increased drive provide the capability to – 2000-V Human-Body Model (A114-A) drive bus lines without interface or pullup – 200-V Machine Model (A115-A) components. – 1000-V Charged-Device Model (C101) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a DESCRIPTION pullup resistor; the minimum value of the resistor is This single D-type latch is designed for 1.65-V to 5.5- determined by the current-sinking capability of the V VCC operation. driver. The SN74LVC1G373 is particularly suitable for This device is fully specified for partial-power-down implementing buffer registers, I/O ports, bidirectional applications using Ioff. The Ioff circuitry disables the bus drivers, and working registers. While the latch- outputs, preventing damaging current backflow enable (LE) input is high, the Q outputs follow the through the device when it is powered down. data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2003–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
Аналогичный номер детали - 74LVC1G373DBVRE4 |
|
Аналогичное описание - 74LVC1G373DBVRE4 |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |