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DAC121S101QML-SP датащи(PDF) 6 Page - Texas Instruments |
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DAC121S101QML-SP датащи(HTML) 6 Page - Texas Instruments |
6 / 26 page DAC121S101QML SNAS410E – MAY 2008 – REVISED MARCH 2013 www.ti.com DAC121S101 Electrical Characteristics AC and Timing Characteristics The following specifications apply for VA = +2.7 V to +5.5 V, RL = ∞, CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified. Sub- Parameter Test Conditions Notes Typical(1) Min Max Units groups fSCLK SCLK Frequency (See Figure 4) See(2) 20 MHz 9, 10, 11 CL ≤ 200 pF 12.5 15 µs 9, 10, 11 FF0 to 00F code change, RL = ∞ CL = 500 pF 12.5 15 µs 9, 10, 11 ts Output Voltage Settling Time CL ≤ 200 pF 12.5 15 µs 9, 10, 11 00Fh to FF0h code change, RL = ∞ CL = 500 pF 12.5 15 µs 9, 10, 11 SR Output Slew Rate See(2) 1 V/µs Code change from 800h to Glitch Impulse See(2) 12 nV-sec 7FFh Digital Feedthrough See(2) 0.5 nV-sec VA = 5 V .65 µs tWU Wake-Up Time See(2) VA = 3 V 1.1 µs 1/fSCLK SCLK Cycle Time (See Figure 4) 50 ns 9, 10, 11 tH SCLK High time (See Figure 4) 20 ns 9, 10, 11 tL SCLK Low Time (See Figure 4) 20 ns 9, 10, 11 Set-up Time SYNC to SCLK tSUCL (See Figure 4) 0 ns 9, 10, 11 Rising Edge tSUD Data Set-Up Time (See Figure 4) 6 ns 9, 10, 11 tDHD Data Hold Time (See Figure 4) 4.5 ns 9, 10, 11 VA = 5.5 V (See Figure 4) 10 ns 9, 10, 11 tCS SCLK fall to rise of SYNC VA = 2.7 V (See Figure 4) 18 ns 9, 10, 11 VA = 5.5 V (See Figure 4) 37 ns 9, 10, 11 tSYNC SYNC High Time VA = 2.7 V (See Figure 4) 36 ns 9, 10, 11 (1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. (2) This parameter is guaranteed by design and/or characterization and is not tested in production. 6 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DAC121S101QML |
Аналогичный номер детали - DAC121S101QML-SP |
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Аналогичное описание - DAC121S101QML-SP |
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