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CDC3RL02 датащи(PDF) 1 Page - Texas Instruments |
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CDC3RL02 датащи(HTML) 1 Page - Texas Instruments |
1 / 20 page V BATT GND MCLK_IN LDO Switch/ Decoder EN V CC V LDO CLK_OUT1 CLK_REQ1 CLK_OUT2 CLK_REQ2 EN V CC Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDC3RL02 SCHS371C – NOVEMBER 2009 – REVISED JANUARY 2016 CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer 1 Features 3 Description The CDC3RL02 is a two-channel clock fan-out buffer 1 • Low Additive Noise: and is ideal for use in portable end-equipment, such – –149 dBc/Hz at 10-kHz Offset Phase Noise as mobile phones, that require clock buffering with – 0.37 ps (RMS) Output Jitter minimal additive phase noise and fan-out capabilities. It buffers a single master clock, such as a • Limited Output Slew Rate for EMI Reduction temperature compensated crystal oscillator (TCXO) (1- to 5-ns Rise/Fall Time for 10-pF to 50-pF to multiple peripherals. The device has two clock Loads) request inputs (CLK_REQ1 and CLK_REQ2), each of • Adaptive Output Stage Controls Reflection which enable a single clock output. • Regulated 1.8-V Externally Available I/O Supply The CDC3RL02 accepts square or sine waves at the • Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP master clock input (MCLK_IN), eliminating the need (0.8 mm × 1.6 mm) for an AC coupling capacitor. The smallest acceptable sine wave is a 0.3-V signal (peak-to- • ESD Performance Exceeds JESD 22 peak). CDC3RL02 has been designed to offer – 2000-V Human-Body Model (A114-A) minimal channel-to-channel skew, additive output – 1000-V Charged-Device Model jitter, and additive phase noise. The adaptive clock (JESD22-C101-A Level III) output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI 2 Applications emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock • Cellular Phones distribution lines. • Global Positioning Systems (GPS) The CDC3RL02 has an integrated Low-Drop-Out • Wireless LAN (LDO) voltage regulator which accepts input voltages • FM Radio from 2.3 V to 5.5 V and outputs 1.8 V, 50 mA. This 1.8-V supply is externally available to provide • WiMAX regulated power to peripheral devices such as a • W-BT TCXO. Simplified Block Diagram The CDC3RL02 is offered in a 0.4-mm pitch wafer- level chip-scale (WCSP) package (0.8 mm × 1.6 mm) and is optimized for very low standby current consumption. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CDC3RL02 DSBGA (8) 0.80 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
Аналогичный номер детали - CDC3RL02_16 |
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Аналогичное описание - CDC3RL02_16 |
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