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CDCDLP223PW датащи(PDF) 3 Page - Texas Instruments |
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CDCDLP223PW датащи(HTML) 3 Page - Texas Instruments |
3 / 10 page www.ti.com ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS RECOMMENDED CRYSTAL SPECIFICATION (1) CDCDLP223 SCAS836 – DECEMBER 2006 over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT VDD Supply voltage range –0.5 to 4.6 V VI Input voltage range(2) –0.5 to VDD + 0.5 V VO Output voltage range(2) –0.5 to VDD + 0.5 V Input current (VI < 0, VI > VDD) ±20 mA IO Continuous output current ±17.5 mA Tstg Storage temperature range –65 to 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. PACKAGE THERMAL IMPEDANCE FOR TSSOP20 PACKAGE(1) Airflow (lfm) θ JA (°C/W) θ JC (°C/W) θ JB (°C/W) Ψ JT (°C/W) 0 83.0 32 54 0.25 150 77.9 – – 250 75.4 – – 500 71.4 – – (1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). MIN NOM MAX UNIT TA Operating free-air temperature -40 85 °C VDD Supply voltage 3.0 3.3 3.6 V VIH High level input voltage SDATA and SCLK 0.7 × V DD VDD V –0.15 0.3 × VIL Low level input voltage SDATA and SCLK V VDD VIL Low level input voltage LVTTL 0.8 V VI thresh Input Voltage threshold LVTTL 1.40 V VIH High level input voltage LVTTL 2.0 V IOH High-level output current LVTTL –8 mA IOL Low-level output current LVTTL 8 mA IOH High-level output current HCLK/HCLK –20 mA IOL Low-level output current HCLK/HCLK 0 mA tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be 0.05 500 ms monotonic) MIN NOM MAX UNIT fxtal Crystal input frequency (fundamental) 20 MHz ESR Effective series resistance 100 Ω Pdrive Maximum power handling (drive level) 100 µW CL Load capacitance 20 pF (1) See DLP™ Control ASIC DDP2230 datasheet for additional requirements. 3 Submit Documentation Feedback |
Аналогичный номер детали - CDCDLP223PW |
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Аналогичное описание - CDCDLP223PW |
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