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CDCM1802RGTR датащи(PDF) 11 Page - Texas Instruments |
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CDCM1802RGTR датащи(HTML) 11 Page - Texas Instruments |
11 / 30 page Div 1 Div 2 Div 4 Div 8 Bias Generator VDD t 1.3 V (imax < 1.5 mA) Control LVPECL LVCMOS IN IN VBB S0 S1 Y1 Y0 Y0 EN CDCM1802 www.ti.com SCAS759B – APRIL 2004 – REVISED NOVEMBER 2015 8 Detailed Description 8.1 Overview The CDCM1802 is a clock buffer with a programmable divider. There is one LVCMOS and one LVPECL output. The LVCMOS output is specifically designed for driving 50- Ω transmission lines. It is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions. Both outputs can be divided individually by 1, 2, 4, and 8. Divider settings can be selected with three 3-level control pins. 8.2 Functional Block Diagram 8.3 Feature Description The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3- level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. For single- ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference. 8.4 Device Functional Modes 8.4.1 Control Pin Settings The CDCM1802 has three control pins, S0, S1, and the enable pin (EN) to select different output mode settings. All three inputs (S0, S1, EN) are 3-level inputs. In addition, the EN input allows disabling all outputs and place them into a Hi-Z (or tristate) output state when pulled to GND. Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: CDCM1802 |
Аналогичный номер детали - CDCM1802RGTR |
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Аналогичное описание - CDCM1802RGTR |
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