поискавой системы для электроныых деталей |
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CDCVF2509PWRG4 датащи(PDF) 5 Page - Texas Instruments |
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CDCVF2509PWRG4 датащи(HTML) 5 Page - Texas Instruments |
5 / 16 page NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT CDCVF2509 www.ti.com SCAS737D – APRIL 2004 – REVISED FEBRUARY 2010 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC, AVCC MIN TYP(1) MAX UNIT VIK Input clamp voltage II = -18 mA 3 V –1.2 V IOH = -100 µA MIN to MAX VCC–0.2 VOH High-level output voltage IOH = -12 mA 3 V 2.1 V IOH = -6 mA 3 V 2.4 IOL = 100 µA MIN to MAX 0.2 VOL Low-level output voltage IOL = 12 mA 3 V 0.8 V IOL = 6 mA 3 V 0.55 VO= 1 V 3 V –28 IOH High-level output current VO = 1.65 V 3.3 V –36 mA VO = 3.135 V 3.6 V -8 VO= 1.95 V 3 V 30 IOL Low-level output current VO = 1.65 V 3.3 V 40 mA VO = 0.4 V 3.6 V 10 II Input current VI = VCC or GND 3.6 V ±5 µA VI = VCC or GND, IO = 0, ICC (2) Supply current (static, output not switching) 3.6 V, 0 V 40 µA Outputs: low or high One input at VCC - 0.6 V, ΔICC Change in supply current 3.3 V to 3.6 V 500 µA Other inputs at VCC or GND Ci Input capacitance VI = VCC or GND 3.3 V 2.5 pF Co Output capacitance VO = VCC or GND 3.3 V 2.8 pF (1) For conditions shown as MIN or MAX, use the appropriate value specified under the recommended operating conditions section. (2) For dynamic ICC vs Frequency, see Figure 8 and Figure 9. SWITCHING CHARACTERISTICS over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF (see Figure 1 and Figure 2) (1) (2) VCC, AVCC = 3.3 V FROM TO ± 0.3 V PARAMETER UNIT (INPUT) (OUTPUT) MIN TYP MAX Phase error time- static (normalized) (see t(f) CLK ↑ = 66 MHz to 166 MHz FBIN ↑ –125 125 ps Figure 3 through Figure 6) tsk(o) Output skew time(3) Any Y Any Y 100 ps Phase error time-jitter (4) CLK = 66 MHz to 100 MHz Any Y or FBOUT –50 50 ps CLK = 66 MHz to 100 MHz -70 Jitter(cycle-cycle) (see Figure 7) Any Y or FBOUT ps CLK = 100 MHz to 166 MHz -65 Duty cycle f(CLK) > 60 MHz Any Y or FBOUT 45% 55% tr Rise time VO = 0.4 V to 2 V Any Y or FBOUT 0.3 1.1 ns/V tf Fall time VO = 2 V to 0.4 V Any Y or FBOUT 0.3 1.1 ns/V Low-to-high propagation delay time, bypass tPLH CLK Any Y or FBOUT 1.8 3.9 ns mode High-to-low propagation delay time, bypass tPHL CLK Any Y or FBOUT 1.8 3.9 ns mode (1) The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. (2) These parameters are not production tested. (3) The tsk(o) specification is only valid for equal loading of all outputs. (4) Calculated per PC DRAM SPEC (tphase error, static-jitter(cycle-to-cycle)). Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): CDCVF2509 |
Аналогичный номер детали - CDCVF2509PWRG4 |
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Аналогичное описание - CDCVF2509PWRG4 |
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