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AD8328ARQ-REEL датащи(PDF) 8 Page - Analog Devices |
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AD8328ARQ-REEL датащи(HTML) 8 Page - Analog Devices |
8 / 16 page REV. 0 –8– AD8328 The output impedance of the AD8328 is 300 Ω, regardless of whether the amplifier is in transmit enable or transmit disable mode. This, when combined with a 2:1 voltage ratio (4:1 imped- ance ratio) transformer, eliminates the need for external back termination resistors. If the output signal is being evaluated using standard 50 Ω test equipment, a minimum loss 75 Ω–50 Ω pad must be used to provide the test circuit with the proper impedance match. The AD8328 evaluation board provides a convenient means to implement a matching attenuator. Soldering a 43.3 Ω resistor in the R15 placeholder and an 86.6 Ω resistor in the R16 placeholder will allow testing on a 50 Ω system. When using a matching attenuator, it should be noted that there will be a 5.7 dB of power loss (7.5 dB voltage) through the network. Power Supply The 5 V supply should be delivered to each of the VCC pins via a low impedance power bus to ensure that each pin is at the same potential. The power bus should be decoupled to ground using a 10 F tantalum capacitor located close to the AD8328. In addition to the 10 F capacitor, each VCC pin should be indi- vidually decoupled to ground with ceramic chip capacitors located close to the pins. The bypass pin, labeled BYP, should also be decoupled. The PCB should have a low impedance ground plane covering all unused portions of the board, except in areas of the board where input and output traces are in close proximity to the AD8328 and the output transformer. All AD8328 ground pins must be connected to the ground plane to ensure proper grounding of all internal nodes. Signal Integrity Layout Considerations Careful attention to printed circuit board layout details will prevent problems due to board parasitics. Proper RF design techniques are mandatory. The differential input and output traces should be kept as short as possible. Keeping the traces short will minimize parasitic capacitance and inductance. This is most critical between the outputs of the AD8328 and the 2:1 output transformer. It is also critical that all differential signal paths be symmetrical in length and width. In addition, the input and output traces should be adequately spaced to minimize coupling (crosstalk) through the board. Following these guide- lines will optimize the overall performance of the AD8328 in all applications. Initial Power-Up When the supply voltage is first applied to the AD8328, the gain of the amplifier is initially set to gain code 1. As power is first applied to the amplifier, the TXEN pin should be held low (Logic 0) to prevent forward signal transmission. After power has been applied to the amplifier, the gain can be set to the desired level by following the procedure provided in the SPI Programming and Gain Adjustment section. The TXEN pin can then be brought from Logic 0 to Logic 1, enabling forward signal transmission at the desired gain level. RAMP Pin and BYP Pin Features The RAMP pin (Pin 15) is used to control the length of the burst on and off transients. By default, leaving the RAMP pin unconnected will result in a transient that is fully compliant with DOCSIS 2.0 Section 6.2.21.2, Spurious Emissions During Burst On/Off Transients. DOCSIS requires that all between burst transients must be dissi- pated no faster than 2 µs. Adding capacitance to the RAMP pin will add more time to the transient. The BYP pin is used to decouple the output stage at midsupply. Typically, for normal DOCSIS operation, the BYP pin should be decoupled to ground with a 0.1 µF capacitor. However, in applications that may require transient on/off times faster than 2 µs, smaller capacitors may be used, but it should be noted that the BYP pin should always be decoupled to ground. Transmit Enable (TXEN) and SLEEP The asynchronous TXEN pin is used to place the AD8328 into between-burst mode. In this reduced current state, the output impedance of 75 Ω is maintained. Applying Logic 0 to the TXEN pin deactivates the on-chip amplifier, providing a 97.8% reduction in consumed power. For 5 V operation, the supply current is typically reduced from 120 mA to 2.6 mA. In this mode of opera- tion, between-burst noise is minimized and high input to output isolation is achieved. In addition to the TXEN pin, the AD8328 also incorporates an asynchronous SLEEP pin, which may be used to further reduce the supply current to approximately 20 µA. Applying Logic 0 to the SLEEP pin places the amplifier into SLEEP mode. Transitioning into or out of SLEEP mode may result in a transient voltage at the output of the amplifier. Distortion, Adjacent Channel Power, and DOCSIS To deliver the DOCSIS required 58 dBmV of QPSK signal and 55 dBmV of 16 QAM signal, the PA is required to deliver up to 60 dBmV. This added power is required to compensate for losses associated with the diplex filter or other passive components that may be included in the upstream path of cable modems or set-top boxes. It should be noted that the AD8328 was characterized with a differential input signal. TPCs 1 and 4 show the AD8328 second and third harmonic distortion performance versus the fundamental frequency for various output power levels. These figures are useful for determining the in-band harmonic levels from 5 MHz to 65 MHz. Harmonics higher in frequency (above 42 MHz for DOCSIS and above 65 MHz for EuroDOCSIS) will be sharply attenuated by the low-pass filter function of the diplexer. Another measure of signal integrity is adjacent channel power, commonly referred to as ACP. DOCSIS 2.0, section 6.2.21.1.1 Table I. Adjacent Channel Power Adjacent Channel Symbol Rate (kSym/s) Channel Symbol Rate (kSym/s) 160 320 640 1280 2560 5120 160 –58 –60 –63 –66 –66 –64 320 –58 –59 –60 –64 –66 –65 640 –60 –58 –59 –61 –64 –65 1280 –62 –60 –59 –60 –61 –63 2560 –64 –62 –60 –59 –60 –61 5120 –66 –65 –62 –61 –59 –60 |
Аналогичный номер детали - AD8328ARQ-REEL |
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Аналогичное описание - AD8328ARQ-REEL |
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