SN54ABT7819

512

× 18 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS305D – AUGUST 1994 – REVISED APRIL 1998

7

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

NAME

I/O

DESCRIPTION

A0–A17

I/O

Port-A data. The 18-bit bidirectional data port for side A.

AF/AEA

O

FIFOA–B almost-full/almost-empty flag. Depth offsets can be programmed for AF/AEA, or the default value of 128 can

be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEA is high when X or fewer words or

(512 – Y) or more words are stored in FIFOA–B. AF/AEA is forced high when FIFOA–B is reset.

AF/AEB

O

FIFOB–A almost-full/almost-empty flag. Depth offsets can be programmed for AF/AEB, or the default value of 128 can

be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEB is high when X or fewer words or

(512 – Y) or more words are stored in FIFOB–A. AF/AEB is forced high when FIFOB–A is reset.

B0–B17

I/O

Port-B data. The 18-bit bidirectional data port for side B.

CLKA

I

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A to its low-to-high transition

and can be asynchronous or coincident to CLKB.

CLKB

I

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B to its low-to-high transition

and can be asynchronous or coincident to CLKA.

CSA

I

Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to either write data from A0–A17 to

FIFOA–B or read data from FIFOB–A to A0–A17. The A0–A17 outputs are in the high-impedance state when CSA

is high.

CSB

I

Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to either write data from B0–B17 to

FIFOB–A or read data from FIFOA–B to B0–B17. The B0–B17 outputs are in the high-impedance state when CSB

is high.

HFA

O

FIFOA–B half-full flag. HFA is high when FIFOA–B contains 256 or more words and is low when FIFOA–B contains

255 or fewer words. HFA is set low after FIFOA–B is reset.

HFB

O

FIFOB–A half-full flag. HFB is high when FIFOB–A contains 256 or more words and is low when FIFOB–A contains

255 or fewer words. HFB is set low after FIFOB–A is reset.

IRA

O

Port-A input-ready flag. IRA is synchronized to the low-to-high transition of CLKA. When IRA is low, FIFOA–B is full

and writes to its array are disabled. IRA is set low during a FIFOA–B reset and is set high on the second low-to-high

transition of CLKA after reset.

IRB

O

Port-B input-ready flag. IRB is synchronized to the low-to-high transition of CLKB. When IRB is low, FIFOB–A is full

and writes to its array are disabled. IRB is set low during a FIFOB–A reset and is set high on the second low-to-high

transition of CLKB after reset.

ORA

O

Port-A output-ready flag. ORA is synchronized to the low-to-high transition of CLKA. When ORA is low, FIFOB–A is

empty and reads from its array are disabled. The last valid word remains on the FIFOB–A outputs when ORA is low.

Ready data is present for the A0–A17 outputs when ORA is high. ORA is set low during a FIFOB–A reset and goes

high on the third low-to-high transition of CLKA after the first word is loaded to an empty FIFOB–A.

ORB

O

Port-B output-ready flag. ORB is synchronized to the low-to-high transition of CLKB. When ORB is low, FIFOA–B is

empty and reads from its array are disabled. The last valid word remains on the FIFOA–B outputs when ORB is low.

Ready data is present for the B0–B17 outputs when ORB is high. ORB is set low during a FIFOA–B reset and goes

high on the third low-to-high transition of CLKB after the first word is loaded to an empty FIFOA–B.

PENA

I

AF/AEA program enable. After FIFOA–B is reset and before a word is written to its array, the binary value on A0–A7

is latched as an AF/AEA offset when PENA is low and CLKA is high.

PENB

I

AF/AEB program enable. After FIFOB–A is reset and before a word is written to its array, the binary value on B0–B7

is latched as an AF/AEB offset when PENB is low and CLKB is high.

RENA

I

Port-A read enable. A high level on RENA enables data to be read from FIFOB–A on the low-to-high transition of CLKA

when CSA is low, W/RA is low, and ORA is high.

RENB

I

Port-B read enable. A high level on RENB enables data to be read from FIFOA–B on the low-to-high transition of CLKB

when CSB is low, W/RB is low, and ORB is high.

RSTA

I

FIFOA–B reset. To reset FIFOA–B, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must

occur while RSTA is low. This sets HFA low, IRA low, ORB low, and AF/AEA high.

RSTB

I

FIFOB–A reset. To reset FIFOB–A, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must

occur while RSTB is low. This sets HFB low, IRB low, ORA low, and AF/AEB high.