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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS4244 датащи(PDF) 10 Page - Cirrus Logic |
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CS4244 датащи(HTML) 10 Page - Cirrus Logic |
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10 / 63 page  DS900F2 10 CS4244 TYPICAL CURRENT CONSUMPTION This table represents the power consumption for individual circuit blocks within the CS4244. CS4244 is configured as shown in Figure 2 on page 8. VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC; FS = 100 kHz; MCLK = 25.6 MHz; DAC load is 3 k ; All input signals are zero (digital zero for SDINx inputs and AC coupled to ground for AINx inputs) . Notes: 8. Full-scale differential output signal. 9. Current consumption increases with increasing FS and increasing MCLK. Values are based on FS of 100 kHz and MCLK of 25.6 MHz. Current variance between speed modes is small. 10. PLL is activated by setting the MCLK RATE bit to either 000 (operating in 256x mode) or 001 (operating in 384kHz). 11. Internal to the CS4244, the analog to digital converters are grouped together in stereo pairs. ADC1 and ADC2 are grouped together as are ADC3 and ADC4. The ADC group current draw is the current that is drawn whenever one of these groups become active. 12. To calculate total current draw for an arbitrary amount of ADCs or DACs, the following equations apply: Total Running Current Draw from VA Supply = Power Down Overhead + PLL (If Applicable)+ DAC Current Draw + ADC Current Draw where DAC Current Draw = DAC Overhead + (Number of DACs x DAC Channel) ADC Current Draw = ADC Overhead + (Number of active ADC Groups x ADC Group) + (Number of active ADC Channels x ADC Channel) and Total Running Current Draw from VL Supply = PDN Overhead + (Number of active ADC Channels x ADC Channel) Typical Current [mA] (unless otherwise noted) (Note 9), (Note 12) Functional Block VA/VL iVA iVL 1 Reset Overhead (All lines held static, RST line pulled low.) 5 0.030 0.001 3.3 0.020 0.001 2 Power Down Overhead (All lines clocks and data lines active, RST line pulled high, All PDNx bits set high.) 5 5 0.101 3.3 5 0.101 3 PLL (Note 10) (Current drawn resulting from PLL being active. PLL is active for 256x and 384x) 51 - 3.3 1 - 4 DAC Overhead (Current drawn whenever any of the four DACs are powered up.) 550 - 3.3 45 - 5 DAC Channel (Note 8) (Current drawn per each DAC powered up.) 55 - 3.3 4 - 6 ADC Overhead (Current drawn whenever any of the four ADCs are powered up.) 511 - 3.3 11 - 7 ADC Group (Current drawn due to an ADC “group” being powered up. See (Note 11)) 52 - 3.3 2 - 8 ADC Channel (Current drawn per each ADC powered up.) 5 2 0.109 3.3 2 0.066 |
Аналогичный номер детали - CS4244 |
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Аналогичное описание - CS4244 |
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