SN74ABT3611

64

× 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCBS127E – JULY 1992 – REVISED APRIL 1998

8

POST OFFICE BOX 655303

synchronized FIFO flags

Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability

by reducing the probability of metastable events on their outputs when CLKA and CLKB operate

asynchronously to one another. FF and AF are synchronized to CLKA. EF and AE are synchronized to CLKB.

Table 4 shows the relationship of the flags to the FIFO.

Table 4. FIFO Flag Operation

NUMBER OF WORDS

IN THE FIFO

SYNCHRONIZED

TO CLKB

SYNCHRONIZED

TO CLKA

IN THE FIFO

EF

AE

AF

FF

0

L

L

H

H

1 to X

H

LH

H

(X + 1) to [64 – (X + 1)]

H

HH

H

(64 – X) to 63

H

HL

H

64

H

H

L

L

† X is the value in the almost-empty flag and almost-full flag offset register.

empty flag (EF)

The FIFO empty flag is synchronized to the port clock that reads data from its array (CLKB). When EF is high,

new data can be read to the FIFO output register. When EF is low, the FIFO is empty and attempted FIFO reads

are ignored.

The FIFO read pointer is incremented each time a new word is clocked to its output register. A word written to

the FIFO can be read to the FIFO output register in a minimum of three port-B clock (CLKB) cycles; therefore,

EF is low if a word in memory is the next data to be sent to the FIFO output register and two CLKB cycles have

not elapsed since the time the word was written. The empty flag of the FIFO is set high by the second low-to-high

transition of CLKB, and the new data word can be read to the FIFO output register in the following cycle.

A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs

cycle (see Figure 4).

full flag (FF)

The FIFO full flag is synchronized to the port clock that writes data to its array (CLKA). When FF is high, an

SRAM location is free to receive new data. No memory locations are free when FF is low and attempted writes

to the FIFO are ignored.

Each time a word is written to the FIFO, its write pointer is incremented. From the time a word is read from the

FIFO, its previous memory location is ready to be written in a minimum of three port-A clock cycles. FF is low

if less than two CLKA cycles have elapsed since the next memory write location has been read. The second

low-to-high transition on CLKA after the read sets FF high and data can be written in the following clock cycle.

A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs

cycle (see Figure 5).