LM3537

SNVS634B – JUNE 2011 – REVISED MAY 2013

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LOGIC INTERFACE CHARACTERISTICS

(1) (2)

Symbol

Parameter

Condition

Min

Typ

Max

Units

SCL (Clock Period)

2.5

µs

Data In Setup Time to SCL High

100

ns

Data Out stable After SCL Low

0

ns

SDA Low Setup Time to SCL Low

100

ns

(Start)

SDA High Hold Time After SCL High

100

ns

(Stop)

Input Logic Low "0"

2.7V

0

0.45

V

Input Logic High "1"

2.7V

1.25

V

Output Logic Low "0"

400

mV

Logic inputs HWEN and PWM

Reset

0

0.45

HWEN Voltage Thresholds

2.7V

V

Normal Operation

1.2

LEDs Off

0

0.45

PWM Voltage Thresholds

2.7V

V

LEDs On

1.2

ALS interrupt

Interrupt Output Logic Low '0'

400

mV

Output Low Level

0.3

0.5

V

Output High Level

V

−0.5

–0.3

(1)

All voltages are with respect to the potential at the GND pins.

(2)

Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most

likely norm.

(3)

SCL and SDA should be glitch-free in order for proper device control to be realized. See Figure 2 for timing specification details.

(4)

SCL is tested with a 50% duty-cycle clock.

(5)

outputs and will reference the high-side to the voltage of SBIAS. '0'; GPOs will act as open-drain outputs (default). In the open-drain

specification is valid only for push-pull -type outputs.

6

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