DW OR NT PACKAGE

(TOP VIEW)

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24

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17

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14

13

OE

1D

2D

3D

4D

5D

6D

7D

8D

9D

CLR

GND

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

9Q

PRE

LE

SN74ALS843

9-BIT BUS-INTERFACE D-TYPE LATCH

WITH 3-STATE OUTPUTS

SDAS232A – DECEMBER 1983 – REVISED JANUARY 1995

Copyright

1

POST OFFICE BOX 655303

Lines Directly

Necessary for Wider Address/Data Paths or

Buses With Parity

dc Loading Effects

Small-Outline (DW) Packages and Standard

Plastic (NT) 300-mil DIPs

description

This 9-bit bus-interface D-type latch features

3-state outputs designed specifically for driving

highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers,

I/O ports, bidirectional bus drivers, and working registers.

The nine latches are transparent D-type latches with noninverting data (D) inputs.

A buffered output-enable (OE) input places the nine outputs in either a normal logic state (high or low logic levels)

or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines

significantly. The high-impedance state and increased drive provide the capability to drive bus lines without

interface or pullup components.

OE does not affect the internal operation of the latches. Previously stored data can be retained or new data can

be entered while the outputs are off.

The SN74ALS843 is characterized for operation from 0

°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUT

PRE

CLR

OE

LE

D

Q

L

X

L

X

X

H

H

LL

X

X

L

H

HL

HL

L

H

HL

H

H

H

H

HL

L

X

Q0

X

X

H

X

X

Z

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.