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SN74ALVC16373DLR датащи(PDF) 1 Page - Texas Instruments

номер детали SN74ALVC16373DLR
подробное описание детали  16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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SN74ALVC16373DLR датащи(HTML) 1 Page - Texas Instruments

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SN74ALVC16373
16BIT TRANSPARENT DTYPE LATCH
WITH 3STATE OUTPUTS
SCAS257B − JANUARY 1993 − REVISED JULY 1995
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
D Member of the Texas Instruments
Widebus
 Family
D EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
D Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D ESD Protection Exceeds 2000 V Per
MIL-STD-833C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit transparent D-type latch is designed
for 3.3-V VCC operation; it is tested at 2.5-V, 2.7-V,
and 3.3-V VCC.
The SN74ALVC16373 is particularly suitable
for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch.
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high-
or low-logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old
data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVC16373 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the
same printed-circuit-board area.
The SN74ALVC16373 is characterized for operation from − 40
°C to 85°C.
DGG OR DL PACKAGE
(TOP VIEW)
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1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
 1995, Texas Instruments Incorporated
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.


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