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UC2726DWPTR датащи(PDF) 4 Page - Texas Instruments |
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UC2726DWPTR датащи(HTML) 4 Page - Texas Instruments |
4 / 7 page UC1726 UC2726 UC3726 PIN DESCRIPTIONS CF: The timing input to the fault logic. A capacitor is placed across the input of CF and ground. The timing win- dow is approximately t = 2.1CFRT. CT: The connection to the timing capacitor that controls the operating frequency. A capacitor to ground is repeti- tively charged during the one shot pulse width. It is dis- charged when a comparator senses zero current in the primary side of the transformer. The one shot pulse width is consequently determined by the time it takes to charge the capacitor from a threshold voltage of VL/4 to VL/2. This pin must be tied to a capacitor. See Recommended Operating Conditions. FAULT: This input to the fault logic initiates the user pro- grammable timer. This time interval, specified by the ca- pacitor on CF, determines the validity of the fault. The pin is tied to a low cost optocoupler, and is high until the UC1727 sends drive information from the PHI pin through the transformer while the FAULT pin stays low. Once this pin goes high, it must stay high during the entire fault win- dow to be accepted as a valid fault. A valid fault sets the FLATCH pin high and prevents the transmitting of gate drive information until the FRESET is toggled high. If fault logic is not used, the FAULT pin must be grounded. FLATCH: A valid fault sets this pin to a logic one and pre- vents the transmitting of gate drive information. The FLATCH pin can only be reset by connecting the FRESET to a logic 0. FRESET: The input to the fault logic that resets the fault logic latch (FLATCH) and enables drive transmit data. This input must be low when powered up and stay low until af- ter the fault latch has been set. GND: The signal and power ground for the device. The power ground of the output transistor is isolated on the chip from the substrate ground which biases the remain- der of the device. OUTA: One output of the two totem pole outputs con- nected across the transformer primary winding. When PHI is high, the output toggles between 0.3V during the one shot charge time and approximately VCC + 0.4V dur- ing the remainder of the period. When PHI is low the out- put toggles between VCC - 2V during the one shot charge time and approximately 0.6VCC during the remainder of the period. OUTB: One output of the two totem pole outputs con- nected across the transformer primary winding. When PHI is high, the output toggles between VCC - 2V during the one shot charge time and approximately 0.6VCC dur- ing the remainder of the period. When PHI is low the out- put toggles between 0.3V during the one shot charge time and approximately VCC + 0.4V during the remainder of the period. PGND: This is the ground for the output transistors bonded in the 28 pin packages. On the sixteen pin pack- ages it is bonded separately to the GND pin. PHI: A logic control input to the isolated gate drive that changes the outputs as described above. This changes the duty cycle of the voltage wave form applied across the transformer. The Isolated High Side IGBT Driver UC1727 senses the different duty cycles as different drive commands. PVCC: This is the input voltage for the output transistors on the 28 pin package. On the sixteen pin packages it is bonded separately to the VCC pin. RT: The input that sets the CT and CF capacitor currents with a resistor to ground. The voltage on RT is approxi- mately 0.3VL. The resulting charge currents are: ICT = ICF = VL / 4RT. SHTDWN: This input shuts down the internal reference. A TTL logic one puts the UC1726 into a low standby current mode. This input has a pull down resistor on the chip to guarantee proper operation when left open. If an external logic voltage is applied to VL, this shutdown feature can- not be used without bringing the external voltage source to zero volts. VCC: The input voltage that biases the outputs and the in- ternal reference. It can vary between 8V to 35V. This sup- ply pin will typically be greater than 28V to be compatible with the UC1727. In order to minimize power dissipation use an external logic supply, VCC approximately 15V, and a step up transformer (N = 2). VL: The logic supply pin that biases all circuits except for the totem pole outputs. A bypass capacitor is recom- mended on this pin when left unconnected. The internal reference is approximately 4.4V. A 5.0V supply can be applied to this pin to assure minimum power dissipation. When an external supply higher than the VL voltage is applied to this pin, the internal reference turns off. Refer to Typical Application on Page 5 and Application Note U-143A "New Chip Pair Provides Isolated Drive for High Voltage IGBTs" 4 |
Аналогичный номер детали - UC2726DWPTR |
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Аналогичное описание - UC2726DWPTR |
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