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UC3714D датащи(PDF) 4 Page - Texas Instruments

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номер детали UC3714D
подробное описание детали  Complementary Switch FET Drivers
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UC1714, UC1715, UC2714
UC2715, UC3714, UC3715
SLUS170B – FEBRUARY 1999 – REVISED MAY 2013
www.ti.com
PIN DESCRIPTIONS
AUX The AUX switches immediately at the rising edge of INPUT’but waits through the T2 delay after the falling
edge of INPUT before switching. AUX is capable of sourcing 0.5 A and sinking 1 A of drive current. See
the Time Relationships diagram below (Figure 1) for the differences between the UC1714 and UC1715 for
INPUT, MAIN, and AUX. During sleep mode, AUX is inactive with a high impedance.
ENBL The ENBL input switches at TTL logic levels (approximately 1.2 V), and the input range is from 0 to 20 V.
The ENBL input places the device into sleep mode when it is a logical low. The current into VCC during
the sleep mode is typically 220
μA.
GND This is the reference pin for all input voltages and the return point for all device currents. GND carries the
full peak sinking current from the outputs. Any tendency for the outputs to ring below GND voltage must
be damped or clamped such that GND remains the most negative potential.
INPUT The input switches at TTL logic levels (approximately 1.4 V) but the allowable range is from 0 to 20 V,
allowing direct connection to most common IC PWM controller outputs. The rising edge immediately
switches the AUX output, and initiates a timing delay, T1, before switching on the PWR output. Similarly,
the INPUT falling edge immediately turns off the PWR output and initiates a timing delay, T2, before
switching the AUX output.
Note that if the input signal comes from a controller with FET drive capability, this signal provides another
option. INPUT and PWR provide a delay only at the leading edge while INPUT and AUX provide the delay
at the trailing edge.
PWR The PWR output waits for the T1 delay after the rising edge of INPUT before switching on, but switches
off immediately at the falling edge of INPUT’(neglecting propagation delays). This output is capable of
sourcing 1 A and sinking 2 A of peak gate-drive current. PWR output includes a passive, self-biased circuit
which holds this pin active low, when ENBL
≤ 0.8V regardless of the voltage of VCC.
T1
A resistor to ground programs the time delay between the AUX switch turnoff and PWR turnon.
T2
This pin functions in the same way as T1 but controls the time delay between PWR turnoff and activation
of the AUX switch.
T1, T2 The resistor on each of these pins sets the charging current on internal timing capacitors to provide
independent time control. The nominal voltage level at each pin is 3 V and the current is internally limited
to 1 mA. The total delay from INPUT to each output includes a propagation delay in addition to the
programmable timer but because the propagation delays are approximately equal, the relative time delay
between the two outputs can be assumed to be solely a function of the programmed delays. The
relationship of the time delay vs. RT is shown in the TYPICAL CHARACTERISTICS curves (see Figure 2).
Either or both pins are alternatively used for voltage sensing in lieu of delay programming, which is done
by pulling the timer pins below their nominal voltage level which immediately activates the timer output.
VCC The VCC input range is from 7 to 20 V. This pin must be bypassed with a capacitor to GND consistent with
peak load current demands.
4
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Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: UC1714 UC1715 UC2714 UC2715 UC3714 UC3715


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