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AD7490BRU датащи(PDF) 4 Page - Analog Devices

номер детали AD7490BRU
подробное описание детали  16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP
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домашняя страница  http://www.analog.com
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AD7490BRU датащи(HTML) 4 Page - Analog Devices

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–4–
AD7490
REV. A
TIMING SPECIFICATIONS1
Limit at TMIN, TMAX
Parameter
VDD = 3 V
VDD = 5 V
Unit
Description
fSCLK
2
10
10
kHz min
16
20
MHz max
tCONVERT
16
tSCLK
16
tSCLK
tQUIET
50
50
ns min
Minimum Quiet Time Required between Bus
Relinquish and Start of Next Conversion
t2
12
10
ns min
CS to SCLK Setup Time
t3
3
20
14
ns max
Delay from
CS until DOUT Three-State Disabled
t3b
4
30
20
ns max
Delay from
CS to DOUT Valid
t4
3
60
40
ns max
Data Access Time after SCLK Falling Edge
t5
0.4 tSCLK
0.4 tSCLK
ns min
SCLK Low Pulsewidth
t6
0.4 tSCLK
0.4 tSCLK
ns min
SCLK High Pulsewidth
t7
15
15
ns min
SCLK to DOUT Valid Hold Time
t8
5
15/50
15/50
ns min/max
SCLK Falling Edge to DOUT High Impedance
t9
20
20
ns min
DIN Setup Time prior to SCLK Falling Edge
t10
55
ns min
DIN Hold Time after SCLK Falling Edge
t11
20
20
ns min
Sixteenth SCLK Falling Edge to
CS High
t12
11
µs max
Power-Up Time from Full Power-Down/
Auto Shutdown/Auto Standby Modes
NOTES
1Sample tested at 25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of 1.6 V.
(See Figure 1.) The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40. The maximum SCLK frequency is 16 MHz with V
DD = 3 V to give a throughput of 870 kSPS. Care must be
taken when interfacing to account for data access time t4, and the setup time required for the user’s processor. These two times will determine the maximum SCLK
frequency with which the user’s system can operate. (See Serial Interface section.)
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 V
DRIVE V.
4t
3b represents a worst-case figure for having ADD3 available on the DOUT line, i.e., if the AD7490 went back into three-state at the end of a conversion and some
other device took control of the bus between conversions, the user would have to wait a maximum time of t3b before having ADD3 valid on DOUT line. If the DOUT
line is weakly driven to ADD3 between conversions, then the user would typically have to wait 17 ns at 3 V and 12 ns at 5 V after the
CS falling edge before seeing
ADD3 valid on DOUT.
5t
8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
(VDD = 2.7 V to 5.25 V, VDRIVE
≤ VDD, REFIN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)


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