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TP3094 датащи(PDF) 6 Page - Texas Instruments |
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TP3094 датащи(HTML) 6 Page - Texas Instruments |
6 / 20 page 6 www.national.com 8-bit Mode In the 8-bit mode, PCM data is transferred inde- pendently for each of the four channels. Each channel has its dedicated transmit and receive frame signals, which determine the time-slots to be taken on the PCM bus. Both short sync and long sync frame are supported. All the channels must have the same FS format (either short or long sync), in case a channel will have a valid frame with different FS format, the device will not function properly. In the short sync, the frame signals must be one bit long; with FSX high during a falling edge of MCLK, the next rising edge of MCLK enables the DX tristate output buffer, which will output the sign bit. The following 7 rising edges clock out the remaining 7 bits, and the next rising edge (9th) disables the DX output. With FSR high during a falling edge of MCLK, the next falling edge of MCLK latches in the sign bit. The following 7 neg- ative edges of MCLK will then latch the remaining 7 bit of the incoming byte. In the long sync frame, the Frame signals must be at least three bits long. The DX output buffer is enabled with the rising edge of FSX or on the ris- ing edge of MCLK, whichever comes later, and the first bit (sign) is clocked out. The following 7 rising edges of MLCK clock out the remaining 7 bits. The DX output is disabled by the 9th rising edge of MCLK. A rising edge on FSR will cause the PCM data at DR to be latched in on the next falling edges of MCLK. For timing diagrams refer to Fig.2, Fig.4, Fig.5 and Fig.6. 32-bit Mode In the 32-bit mode, the four PCM data bytes of the four channels are treated as a single 32-bit data word. The PCM transfer is started by the positive pulses on the transmit or receive frame sync (FSX0, FSR0) inputs. The following 32 negative edges of MCLK will then latch the input PCM data at DR, for all 4 channel starting from channel 0; while the positive edges will clock out the transmit PCM data at DX, from channel 0 to channel 3. In this mode the pins FSX1 and FSR1 become the frame signal carry-out signals, providing a single- bit-long frame pulse during the last bit of the 32- bit stream and allowing another TP3094 to be connected in 32-bit mode. In case any channel is powered down (through the PDN pin) during its assigned time slot the DX pin will be set in tristate and the DR signal will be ignored. In case all the channels are placed in power down, the device will still generate the FS carry output on FSX1, FSR1. For timing diagrams refer to Fig.7 and Fig.8. Test Modes The TP3094 includes the following test modes • digital loopback • analog loopback • DC conversion These modes can be programmed per channel or for all 4 channels simultaneously. The device is programmed into any test mode by exercising the pins TST, PDN0, PDN1, PDN2, PDN3 together. The signals to this pins must be stable for at least 16 MCLK cycles before the de- vice enters any selected test mode. When exiting the test mode, the PDN must return to the previ- ous state to resume the original operating state. During any test mode (TST=1), it will not be pos- sible to change the PU/PD state for any channel not involved in the test mode configuration (e.g. not in test mode). The channel(s) under test must be placed in power up prior the test mode selec- tion, in case left in power down, any programmed test mode will not be operational. When the device exits the test mode, normal op- eration will return, and the PU/PD programmabil- ity will be available, by the state of the PDN signals. The programming of the test modes is according to the table below. The digital loopback is a bit true feedback from the PCM highway to the PCM highway, per- formed exactly at the PCM internal interface. Each byte is looped back from RX to TX on the programmed time slot (FS). The analog output is forced to 0Vac level (typically 2.4Vdc), with low output impedance. The analog loopback is performed from the out- put of the D/A converter (before the output ampli- fier) and the input of the A/D, so the RX signal is looped back towards the TX direction, through the device. The analog output is at 0Vac level, with high output impedance. In the DC conversion mode, the channel under test is programmed to transfer any DC signal (within the available range) in the TX direction, from the analog GXO to the DX digital output, by Functional Description (continued) |
Аналогичный номер детали - TP3094_12 |
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Аналогичное описание - TP3094_12 |
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