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TPD1E10B06-Q1 датащи(PDF) 9 Page - Texas Instruments |
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TPD1E10B06-Q1 датащи(HTML) 9 Page - Texas Instruments |
9 / 18 page 9 TPD1E10B06-Q1 www.ti.com SLVSDN7A – AUGUST 2016 – REVISED AUGUST 2016 Product Folder Links: TPD1E10B06-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Feature Description (continued) 7.3.6 Dynamic Resistance The IO pins feature an ESD clamp that has a low RDYN of 0.32 Ω (Pin 1 to Pin 2) and 0.38 Ω (Pin 2 to Pin 1) which prevents system damage during ESD events. 7.3.7 DC Breakdown Voltage The DC breakdown voltage between the IO pins is a minimum of 6 V. This ensures that sensitive equipment is protected from surges above the reverse standoff voltage of 5.5 V. 7.3.8 Ultra Low Leakage Current The IO pins feature an ultra-low leakage current of 100 nA (maximum) with a bias of 5 V. 7.3.9 Clamping Voltage The IO pins feature an ESD clamp that is capable of clamping the voltage to 10 V (IPP = 1 A) and 14V (IPP = 5 A). 7.3.10 Industrial Temperature Range This device features an industrial operating range of –40°C to +125°C 7.3.11 Space-Saving Footprint This device features a space-saving, industry standard 0402 footprint. 7.4 Device Functional Modes The TPD1E10B06-Q1 is a passive clamp that has low leakage during normal operation when the voltage between pin 1 and pin 2 is below VRWM and activates when the voltage between pin 1 and pin 2 goes above VBR. During IEC ESD events, transient voltages as high as ±30 kV can be clamped between the two pins. When the voltages on the protected lines fall below the trigger voltage, the device reverts back to the low leakage passive state. |
Аналогичный номер детали - TPD1E10B06-Q1 |
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Аналогичное описание - TPD1E10B06-Q1 |
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