TPS3813J25, TPS3813L30, TPS3813K33, TPS3813I50

PROCESSOR SUPERVISORY CIRCUITS WITH WINDOW-WATCHDOG

SLVS331A – DECEMBER 2000 – REVISED APRIL 2001

8

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDD = 2 V to 6 V,

IOL = 500 µA

0.2

VOL

Low

VDD = 3.3 V

IOL = 2 mA

0.4

V

VDD = 6 V,

IOL = 4 mA

0.4

Power up reset voltage (see Note 2)

VDD ≥ 1.1 V,

IOL= 50 µA

0.2

V

TPS3813J25

2.2

2.25

2.3

V

VIT

Negative

TPS3813L30

TA = 40°C 85°C

2.58

2.64

2.7

VIT

g

gg

voltage (see Note 3)

TPS3813K33

TA = –40°C – 85°C

2.87

2.93

3

TPS3813I50

4.45

4.55

4.65

TPS3813J25

30

Hysteresis

TPS3813L30

35

mV

Vhys

Hysteresis

TPS3813K33

40

mV

TPS3813I50

60

WDI, WDR

WDI = VDD = 6 V, WDR = VDD = 6 V

–25

25

IIH

High-level input current

WDT

WDT = VDD = 6 V, VDD > VIT

RESET = High

–100

100

nA

IIL

Low level input current

WDI, WDR

WDI = 0 V, WDR = 0 V, VDD = 6 V

–25

25

nA

IIL

Low-level input current

WDT

WDT = 0 V, VDD > VIT, RESET = High

–100

100

IOH

High-level output current

VDD = VIT + 0.2 V, VOH = VDD

25

nA

IDD

Supply current

VDD = 2 V output unconnected

9

13

µA

IDD

Supply current

VDD = 5 V output unconnected

20

25

µA

Ci

Input capacitance

VI = 0 V to VDD

5

pF

NOTES:

2. The lowest supply voltage at which RESET becomes active. tr,VDD ≥ 15 µs/V.

3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1

µF) should be placed near to the supply terminals.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tw

Pulse width at VDD

VDD = VIT– + 0.2 V, VDD = VIT– – 0.2 V

3

µs

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td

Delay time

VDD ≥ VIT + 0.2 V, See timing diagram

20

25

30

ms

WDT = 0 V

0.2

0.25

0.3

s

tt(out) Watchdog time-out

Upper limit

WDT = VDD

2

2.5

3

s

tt(out) Watchdog time-out

Uer limit

WDT = programmable (see Note 4)

See

Note 5

ms

WDR = 0 V, WDT = 0 V

1:31.8

WDR = 0 V, WDT = VDD

1:32

Watchdog window ratio

WDR = 0 V, WDT = programmable

1:25.8

Watchdog window ratio

WDR = VDD, WDT = 0 V

1:124.9

WDR = VDD, WDT = VDD

1:127.7

WDR = VDD, WDT = programmable

1:64.5

tPHL

Propagation (delay) time,

high-to-low-level output

VDD to RESET delay

VIL = VIT – 0.2 V, VIH = VIT + 0.2 V

30

50

µs

NOTES:

4. 155 pF

< C(ext) < 63 nF

5. (C(ext) ÷ 15.55 pF + 1) x 6.25 ms