TPS40050

TPS40051

TPS40053

SLUS540F − DECEMBER 2002 − REVISED JUNE 2004

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5

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

BOOST

14

O

Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the input voltage.

A 0.1-

µF ceramic capacitor should be connected from this pin to the drain of the lower MOSFET.

BP5

3

O

5-V reference. This pin should be bypassed to ground with a 0.1-

µF ceramic capacitor. This pin may be used with

an external DC load of 1 mA or less.

BP10

11

O

10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-

µF

ceramic capacitor. This pin may be used with an external DC load of 1 mA or less.

COMP

8

O

Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the

VFB pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to improve

large signal transient response.

HDRV

13

O

Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW

(MOSFET off).

ILIM

16

I

Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a voltage

drop across an external resistor connected from this pin to VCC. The voltage on this pin is compared to the voltage

drop (VIN −SW) across the high side MOSFET during conduction.

KFF

1

I

A resistor is connected from this pin to VIN to program the amount of voltage feed-forward. The current fed into

this pin is internally divided and used to control the slope of the PWM ramp.

LDRV

10

O

Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground

(MOSFET off).

PGND

9

−

Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of

the lower MOSFET(s).

RT

2

I

A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.

SGND

5

−

Signal ground reference for the device.

SS/SD

6

I

Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The

capacitor is charged with an internal current source of 2.3

µA. The resulting voltage ramp on the SS pin is used

as a second non-inverting input to the error amplifier. The output voltage begins to rise when VSS/SD is

approximately 0.85 V. The output continues to rise and reaches regulation when VSS/SD is approximately 1.55 V.

The controller is considered shut down when VSS/SD is 125 mV or less. All internal circuitry is inactive. The internal

circuitry is enabled when VSS/SD is 210 mV or greater. When VSS/SD is less than approximately 0.85 V, the outputs

cease switching and the output voltage (VOUT) decays while the internal circuitry remains active.

SW

12

I

This pin is connected to the switched node of the converter and used for overcurrent sensing. The TPS40050 and

TPS40053 versions use this pin for zero current sensing as well.

SYNC

4

I

Syncronization input for the device. This pin can be used to synchronize the oscillator to an external master

frequency. If synchronization is not used, connect this pin to SGND.

VFB

7

I

Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference

voltage, 0.7 V.

VIN

15

I

Supply voltage for the device.