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FAN5068MPX датащи(PDF) 10 Page - Fairchild Semiconductor |
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FAN5068MPX датащи(HTML) 10 Page - Fairchild Semiconductor |
10 / 18 page PRODUCT SPECIFICATION FAN5068 10 REV. 1.0.1 9/9/04 Figure 6. Start-up Sequence into S0. VDDQ 5V SB V(UVLO) 4V 1V 3.3V LDO T0 3.8V T1 T2 T3 T4 T5 PWM Regulator A PSPICE model and spreadsheet calculator are available for the VDDQ PWM regulator to select external components and verify loop stability. The topics covered below provide the explanation behind the calculations in the spreadsheet. Setting the output voltage The output voltage of the PWM regulator can be set in the range of 0.9V to 90% of its power input by an external resis- tor divider. The internal reference is 0.9V. The output is divided down by an external voltage divider to the FB pin (for example, R1 and R2 in Figure 1). There is also a 1µA precision (±5%) current sourced out of FB to ensure that if the pin is open, VDDQ will remain low. The output voltage therefore is: To minimize noise pickup on this node, keep the resistor to GND (R2) below 2k. We selected R2 at 1.82k and solved for R1. The synchronous buck converter is optimized for 5V opera- tion. The PWM modulator uses an average current mode control for simplified feedback loop compensation. Oscillator The oscillator frequency is 300kHz. The internal PWM ramp is reset on the rising clock edge. PWM Soft Start When the PWM regulator is enabled the circuit will wait until the VDDQ IN pin is below 100mV to ensure that the soft-start cycle does not begin with a large residual voltage on the PWM regulator output. When the PWM regulator is disabled, 50 Ω is turned on from VDDQ IN to PGND to discharge the output. The voltage at the positive input of the error amplifier is limited to VCSS which is charged with a 50µA current source. Once CSS has charged to 0.9V, the output voltage will be in regulation. The time it takes SS to reach 0.9V is: where T0.9 is in ms if CSS is in nF. CSS charges another 400mV before the PWM regulator’s latched faults are enabled. When CSS reaches 2.5V, the VTT and 1.2V LDO will begin their soft-start ramps. After the VTT and 1.2V LDO regulators are in regulation, PGOOD is then allowed to go HIGH (open). UVLO on VCC will discharge SS and reset the IC. To prevent large duty cycles and high currents during the beginning of the PWM soft-start, the input to the PWM com- parator is also clamped by CSS. This clamping action has no practical effect on operation of the circuit after CSS has passed about 0.4V. 0.9V R2 ------------ V OUT 0.9V – R1 ---------------------------------1 µA + = (3a) R1 R2 V OUT 0.9 – () • 0.9 1 µA – ---------------------------------------------- 1.816k 1.82k ≈ == (3b) T 0.9 0.9 C SS × 50 ----------------------- = (4) |
Аналогичный номер детали - FAN5068MPX |
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Аналогичное описание - FAN5068MPX |
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