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TLA5203 датащи(PDF) 2 Page - List of Unclassifed Manufacturers

номер детали TLA5203
подробное описание детали  LOGIC ANALYZERS
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TLA5000 Series Logic Analyzers
TLA5201 • TLA5202 • TLA5203 • TLA5204
Logic Analyzers • www.tektronix.com/logic_analyzers
2
Characteristics
General
Number of Channels –
(All channels are acquired including clocks.)
TLA5201: 34 channels (2 are clock channels).
TLA5202: 68 channels (4 are clock channels).
TLA5203: 102 channels (4 are clock and 2 are
qualifier channels).
TLA5204: 136 channels (4 are clock and 4 are
qualifier channels).
Time Stamp – 51-Bits at 125 ps resolution
(3.25 days duration).
Clocking/Acquisition Modes –
Internal, internal 2X, internal 4X, external, external
2X, source synchronous. 125 ps (8 GHz) MagniVu
high-speed timing is available simultaneous with
all modes.
Input Characteristics (with
P6417, P6418, P6419 or
P6434 probes)
Capacitive Loading –
<0.7 pF typical data/clock (P6419).
1.4 pF typical data; 2 pF typical clock (P6418).
2 pF typical data/clock (P6417, P6434).
Threshold Selection Range – From –2.0 V to
+4.5 V in 5 mV increments. Threshold presets
include TTL (1.5 V), CMOS (1.65 V), ECL (–1.3 V),
PECL (3.7 V), LVPECL (2.0 V), LVCMOS 1.5 V
(0.75 V), LVCMOS 1.8 V (0.9 V), LVCMOS 2.5 V
(1.25 V), LVCMOS 3.3 V (1.65 V), LVDS (0 V) and
user-defined.
Threshold Selection Channel Granularity –
Separate selection for each of the clock/qualifier
channels and one per group of 16 data channels.
Threshold Accuracy (including probe) – ±(100 mV)
Input Voltage Range –
Operating: –2.5 V to 5.0 V.
Nondestructive: ±15 V.
Minimum Input Signal Swing –
±250 mV (P6417, P6418, P6419).
±300 mV (P6434).
Input Signal Minimum Slew Rate –
200 mV/ns typical.
State Acquisition
Characteristics (with P6417,
P6418, P6419 or P6434 probes)
Maximum State Clock Rate – 235 MHz.
Maximum State Data Rate – 470 Mb/s.
State Memory Depth with Timestamps (half/full
channels) – 1 Mb/512 Kb, 4/2 Mb, 16/8 Mb.
Setup and Hold Time Selection Range – 16 ns
range that may be shifted towards the setup region
by 0 ns [+8, –8] ns, 4 ns [+12, –4] ns, or 8 ns
[+16, 0] ns.
Setup-and-hold Window – All Channels: 1.5 ns
typical.
Minimum Clock Pulse Width –
1.5 ns (P6434).
1.25 ns (P6417, P6418, P6419).
Demux Channel Selection – Channels can be
demultiplexed to other channels through user
interface with 8 channel granularity.
Timing Acquisition
Characteristics (with P6417,
P6418, P6419 or P6434 probes)
MagniVuTiming – 125 ps (8 GHz). Storage rate
adjustable to 250 ps, 500 ps, 1 ns and 2 ns.
MagniVu Timing Memory Depth – 16 Kb per
channel, with adjustable trigger position.
Deep Memory Timing Resolution
(quarter/half/full channels) – 500 ps/1 ns/2 ns
to 50 ms.
Deep Memory Timing Memory Depth
(quarter/half/full channels with timestamps and
with or without transitional storage) – 2 Mb/
1 Mb/512 Kb, 8/4/2 Mb, 32/16/8 Mb per channel.
Deep Memory Timing Memory Depth with
Glitch Storage Enabled – Half of default main
memory depth.
Channel-to-channel Skew – 1 ns. 900 ps typical.
Minimum Recognizable Pulse/Glitch Width
(single channel) – 1 ns (P6417, P6418, P6419)
1.25 ns (P6434).
Minimum Detectable Setup/Hold Violation –
250 ps.
Minimum Recognizable Multi-channel Trigger
Event – Sample period + channel-to-channel skew.
Trigger Characteristics
Independent Trigger States – 16.
Maximum Independent If/Then Clauses
per State – 16.
Maximum Number of Events per If/Then
Clause – 8
Maximum Number of Actions per If/Then
Clause – 8.
Maximum Number of Trigger Events – 18 (2
counter/timers plus any 16 other resources).
Number of Word Recognizers – 16.
Number of Transition Recognizers – 16.
Number of Range Recognizers – 4.
Number of Counter/Timers – 2.
Trigger Event Types – Word, group, channel, tran-
sition, range, anything, counter value, timer value,
signal, glitch, setup-and-hold violation, snapshot.
Trigger Action Types – Trigger main, trigger
MagniVu, store, don’t store, start store, stop store,
increment counter, decrement counter, reset counter,
start timer, stop timer, reset timer, snapshot current
sample, goto state, set/clear signal, do nothing.
Trigger Sequence Rate – DC to 500 MHz (2 ns).
Counter/Timer Range – 51 Bits each (>50 days
at 2 ns).
Counter Rate – DC to 500 MHz (2 ns).
Timer Clock Rate – 500 MHz (2 ns).
Counter/Timer Latency – 2 ns.
Range Recognizers – Double bounded (can be as
wide as any group, must be grouped according to
specified order of significance).
Setup-and-Hold Violation Recognizer Setup Time
Range – From 8 ns before to 7.5 ns after clock
edge in 125 ps increments.
Setup-and-Hold Violation Recognizer Hold Time
Range – From 7.5 ns before to 8 ns after clock
edge in 125 ps increments.
Trigger Position – Any data sample.
MagniVu Trigger Position – MagniVu position can
be set from 0% to 60% centered around the
MagniVu trigger.
Storage Control (data qualification) – Global
(conditional), by state (start/stop), block, by trigger
action or transitional. Force main prefill selection
available.
TLA5000 Series with TDS5000 Series
Oscilloscope.


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